Data-driven topology design for conductor layout problem of electromagnetic interference filter
Duanyutian Zhou, Nomura Katsuya, Shintaro Yamasaki
TL;DR
Data-driven topology design (DDTD) addresses conductor-layout optimization for EMI filters where parasitics such as ESL and ESR strongly influence performance, and traditional topology optimization struggles with nonlinear, multi-objective objectives. The method combines a deep generative model with elite data selection to produce high-DOF conductor layouts in a sensitivity-free framework, while enforcing a simple constraint to preserve the circuit topology. Numerical demonstrations on π-type EMI filters show that DDTD can discover complex layouts that substantially reduce ESL and ESR, improving $S_{21}$ at high frequencies, and that topology preservation is crucial to avoid meaningless designs. This work provides a practical, data-driven pathway for robust EMI-filter design and motivates further extensions to multi-frequency objectives and manufacturability considerations.
Abstract
Electromagnetic interference (EMI) filters are used to reduce electromagnetic noise. It is well known that the performance of an EMI filter in reducing electromagnetic noise largely depends on its conductor layout. Therefore, if a conductor layout optimization method with a high degree of freedom is realized, a drastic performance improvement is expected. Although there are a few design methods based on topology optimization for this purpose, these methods have some difficulties originating from topology optimization. In this paper, we therefore propose a conductor layout design method for EMI filters on the basis of data-driven topology design (DDTD), which is a high degree of freedom structural design methodology incorporating a deep generative model and data-driven approach. DDTD was proposed to overcome the intrinsic difficulties of topology optimization, and we consider it suitable for the conductor layout design problem of EMI filters. One significant challenge in applying DDTD to the conductor layout design problem is maintaining the topology of the circuit diagram during the solution search. For this purpose, we propose a simple yet efficient constraint. We further provide numerical examples to confirm the usefulness of the proposed method.
