A 10.60 $μ$W 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection

TL;DR

An ultra-low power, mixed-bit-width sparse convolutional neural network (CNN) accelerator to accelerate ventricular arrhythmia (VA) detection and achieves 50% sparsity in a quantized 1D CNN using a sparse processing element (SPE) architecture is proposed.

Abstract

This paper proposes an ultra-low power, mixed-bit-width sparse convolutional neural network (CNN) accelerator to accelerate ventricular arrhythmia (VA) detection. The chip achieves 50% sparsity in a quantized 1D CNN using a sparse processing element (SPE) architecture. Measurement on the prototype chip TSMC 40nm CMOS low-power (LP) process for the VA classification task demonstrates that it consumes 10.60 $μ$W of power while achieving a performance of 150 GOPS and a diagnostic accuracy of 99.95%. The computation power density is only 0.57 $μ$W/mm$^2$, which is 14.23X smaller than state-of-the-art works, making it highly suitable for implantable and wearable medical devices.

Figures (4)

• Figure 1: Architecture of the Proposed CNN Accelerator.
• Figure 2: Area-Power-Efficiency SPE Architecture with Single SPad method.
• Figure 3: Mixed-bit Signed Reconfigurable Multiplier (CMUL) Architecture.
• Figure 4: Die Micrograph and the AC Codesign-V1 Platform Demonstration.