Engineering Bosonic Codes with Quantum Lattice Gates

TL;DR

To address fault-tolerant quantum computation with bosonic codes, the paper introduces a universal single-type gate, the quantum lattice gate, implemented via Floquet Hamiltonian engineering. It provides an analytic framework to engineer code states and transitions directly from target states, enabling code-state preparation, code-space embedding, and code-space transformation through sequences of PSL gates. The method is demonstrated on single-binomial code states, binomial-to-cat code transformations, and automatic quantum error correction against single-photon loss in cat codes, with explicit results shown in Wigner functions and noncommutative Fourier coefficients. The approach is tailored for superconducting circuit QED using Josephson junction nonlinearity, enabling sub-nanosecond gates and offering a scalable path toward fault-tolerant bosonic quantum computation.

Abstract

Bosonic codes offer a hardware-efficient approach to encoding and protecting quantum information with a single continuous-variable bosonic system. In this paper, we introduce a new universal quantum gate set composed of only one type of gate element, which we call the quantum lattice gate, to engineer bosonic code states for fault-tolerant quantum computing. We develop a systematic framework for code state engineering based on the Floquet Hamiltonian engineering, where the target Hamiltonian is constructed directly from the given target state(s). We apply our method to three basic code state engineering processes, including single code state preparation, code space embedding and code space transformation. We explore the application of our method to automatic quantum error correction against single-photon loss with four-legged cat codes. Our proposal is particularly well-suited for superconducting circuit architectures with Josephson junctions, where the full nonlinearity of Josephson junction potential is harnessed as a quantum resource and the quantum lattice gate can be implemented on a sub-nanosecond timescale.

Figures (10)

• Figure 1: Quantum lattice gate. (a) Quantum circuit of a phase-space lattice (PSL) gate decomposed into one x-space lattice (XSL) gate and two phase rotation gates $\mathrm{R(\pm\theta)}$, cf. Eq. (\ref{['eq-PXSL']}). The upper and lower lines of circuit represent the bosonic state stored in the cavity and the external driving field exerted on the cavity, respectively. (b) Schematic illustration of implementing the PSL gate with a harmonic oscillator with bare frequency $\omega_0$ kicked by a cosine-lattice potential (left). The kick exerted at time moment $t=\theta/\omega_0$ realizes the XSL gate $e^{i\gamma \cos(\rho x+\delta)}$; the free evolutions of oscillator before and after the kick realize the phase rotation gates $\mathrm{R(\theta)}$ and $\mathrm{R(-\theta)}$, respectively (right).
• Figure 2: Wigner functions of bosonic code states $W(x,p)$. (a)-(b) Two logical cat code states $|\bar{0}_{c}\rangle$ and $|\bar{1}_{c}\rangle$ defined in Eq. (\ref{['eq-sm-4cat']}) for the first "sweet spot" ($\alpha^2\approx 2.34$) determined by Eq. (\ref{['eq-sm-kl']}). (c)-(d) Two logical binomial code states $|\bar{0}_{b}\rangle$ and $|\bar{1}_{b}\rangle$ defined in Eq. (\ref{['eq-bin']}).
• Figure 3: Code states engineering. (a) Code state preparation (CStP) and Code space embedding (CSpE) via adiabatic ramp (AR) from the bare cavity Hamiltonian $\hat{H}_0$ to the target Hamiltonian $\hat{H}_T$ construct by Eq. (\ref{['eq-Hf']}) and Eq. (\ref{['eq-HTembed']}) respectively. (b) Code space transformation (CSpT) from the binomial Hamiltonian $\hat{H}_{bin}$ to the cat Hamiltonian $\hat{H}_{cat}$ via a transit Hamiltonian $\hat{H}_t$, cf. Eqs. (\ref{['eq-Htran']})--(\ref{['eq-Hbc']}).
• Figure 4: Quantum lattice gate decomposition. (a) Chart of driving field modulation, representing the amplitude $A(k_n,t)$ or the phase $\phi(k_n,t)$, over a single Floquet period $T=2\pi/\omega_0$. The whole chart is divided into $N\times M$ grids. Each grid is labelled by $\{k_n=n\Delta k, t_m=m\Delta t\}$ corresponding to a discrete unitary time evolution $\mathrm{PSL}(k_n,t_m)$ that is defined as the grid lattice gate, cf. Eqs. (\ref{['eq-Ukntm']})--(\ref{['eq-pslnm']}). The $\mathrm{t_m\hbox{-}PSL}$ gate is composed by concatenating grid lattice gates along the row for a fixed time $t_m$, cf. Eq. (\ref{['eq-PLLtm']}). (b) Quantum circuits of lattice gate decomposition: (upper) the whole code state engineering process is decomposed into a sequence of $\mathrm{\Xi}(\beta,\Omega)$ lattice gates, cf. Eq. (\ref{['eq-FloqsT']}); (middle) each $\mathrm{\Xi}(\beta,\Omega)$ gate is decomposed into a sequence of $\mathrm{t_m\hbox{-}PSL}$ gates, cf. Eq. (\ref{['eq-PLLtm']}); (lower) a single $\mathrm{t_m\hbox{-}PSL}$ gate is decomposed into a sequence of grid lattice gates $\mathrm{PSL}(k_n,t_m)$ shown in (a).
• Figure 5: State preparation of a single binomial code. (a) Q-function of target Hamiltonian $H^Q_T(x,p)=-\Delta\langle \alpha |\psi_{T}\rangle\langle \psi_{T}|\alpha \rangle$ with $|\psi_{T}\rangle=(|\bar{0}_b\rangle+\sqrt{3}|\bar{1}_b\rangle)/2$. (b) Charts of driving amplitude $A(k,t)$ (left) and driving phase $\phi(k,t)$ (right) for the engineered driving potential, cf. Eqs. (\ref{['eq-Vxt-2']}) and (\ref{['eq-Aphi']}), for the target Hamiltonian $|\psi_{T}\rangle$. (c) Snapshots of Wigner functions of prepared state $W(x,p)$ during the adiabatic ramp process at different time moments. (d) Time evolution of infidelity of the prepared state with respect to the target state $|\psi_{\text{T}}\rangle$ given by $1-F_{pre}(t)$, where the fidelity $F_{pre}(t)$ is calculated from Eq. (\ref{['eq-fidelity']}). (e) Envelopes of driving amplitude $\beta(t)$ and driving frequency $\omega(t)$ during the adiabatic ramp process, cf. Eqs. (\ref{['rampH']})--(\ref{['protocol1']}). Parameters: $\lambda=0.25\omega_{0}$, $\Delta=1.3\omega_{0}$, $\beta_{f}=0.02\omega_{0}$, $\omega(0)=\omega_{0}/(1+\pi\times10^{-3})$, $s_{1}=40/t_{f}$, $s_{2}=30/t_{f}$, $t_{c,1}=t_{f}/6$, $t_{c,2}=2t_{f}/3$.