Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

A 0.03${mm}^2$ 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing

Yudhajit Ray, Archisman Ghosh, Shreyas Sen

TL;DR

This paper presents a unique implementation of integrating sub-sampling phase locked loop, which alleviates the usage of additional gain elements in the PLL and reduces the noise injection in the system.

Abstract

Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and accurate clock generation are of the utmost importance. This paper presents a unique implementation of integrating sub-sampling phase locked loop, which alleviates the usage of additional gain elements in the PLL and reduces the noise injection in the system. In this design, the ring oscillator-based PLL can operate a wide frequency range of 100-250MHz while consuming 0.03mm2 of area and 131.8$μW$ of power at 250MHz. The area-normalized figure of merit (FOM) of the integrating SSPLL is found to be -236, while showing a reference spur of -43.2dB.

A 0.03${mm}^2$ 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing

TL;DR

This paper presents a unique implementation of integrating sub-sampling phase locked loop, which alleviates the usage of additional gain elements in the PLL and reduces the noise injection in the system.

Abstract

Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and accurate clock generation are of the utmost importance. This paper presents a unique implementation of integrating sub-sampling phase locked loop, which alleviates the usage of additional gain elements in the PLL and reduces the noise injection in the system. In this design, the ring oscillator-based PLL can operate a wide frequency range of 100-250MHz while consuming 0.03mm2 of area and 131.8 of power at 250MHz. The area-normalized figure of merit (FOM) of the integrating SSPLL is found to be -236, while showing a reference spur of -43.2dB.

Paper Structure

This paper contains 11 sections, 9 figures.

Table of Contents

  1. Introduction
  2. Background and Relevant Work
  3. INTEGRATING SUB-SAMPLING PLL
  4. Operating Principle
  5. Overall Architecture
  6. Integrating Sub-sampling Phase Detector
  7. Loop Filter
  8. Pseudo-differential RC Ring Oscillator
  9. Digital Frequency Locked Loop
  10. measurement results
  11. conclusions and future work

Figures (9)

  • Figure 1: Frequency vs. Power Consumption of State-of-the-art PLL Implementations and Target Applications for this design
  • Figure 2: Sub-sampling PLL Architectures and Sub-sampling Phase Detector Architectures for (a) Conventional, (b) AMASSPLL b5, and (c) CSPLL b6
  • Figure 3: Primary advantage of ISSPD over other SSPD architectures
  • Figure 4: (a) Circuit diagram, (b) operating principle and timing diagram, and (c) phase detection gain analysis of the implemented ISSPD
  • Figure 5: Overall Architecture of Integrating Sub-sampling PLL
  • ...and 4 more figures