Table of Contents
Fetching ...

SAIM: Scalable Analog Ising Machine for Solving Quadratic Binary Optimization Problems

Sasan Razmkhah, Jui-Yu Huang, Mehdi Kamal, Massoud Pedram

TL;DR

A CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs) using 12nm FinFET technology using the Cadence Virtuoso.

Abstract

This paper presents a CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs). In the designed LHZ tile, the voltage-controlled oscillators are employed as the physical Ising spins, while for the ancillary spins, we introduce an oscillator-based circuit to emulate the constraint needed to ensure the correct functionality of the tile. We implement the proposed LHZ tile in 12nm FinFET technology using the Cadence Virtuoso. Simulation results show the proposed tile could converge to the results in about 31~ns. Also, the designed spins could operate at approximately 13~GHz.

SAIM: Scalable Analog Ising Machine for Solving Quadratic Binary Optimization Problems

TL;DR

A CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs) using 12nm FinFET technology using the Cadence Virtuoso.

Abstract

This paper presents a CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs). In the designed LHZ tile, the voltage-controlled oscillators are employed as the physical Ising spins, while for the ancillary spins, we introduce an oscillator-based circuit to emulate the constraint needed to ensure the correct functionality of the tile. We implement the proposed LHZ tile in 12nm FinFET technology using the Cadence Virtuoso. Simulation results show the proposed tile could converge to the results in about 31~ns. Also, the designed spins could operate at approximately 13~GHz.

Paper Structure

This paper contains 8 sections, 3 equations, 8 figures, 1 table.

Figures (8)

  • Figure 1: The annealing process of a leaky oscillator network is demonstrated. If the rate of power gain does not exceed the rate of power loss for any state, none of these states can be sustained, and noise will dominate. The first stable state to emerge is the one with the smallest loss. Due to the mapping from loss to the figure-of-merit, this physical state encodes the global minimum of the problem.
  • Figure 2: Converting a 4-node all-to-all connected graph to the LHZ architecture. Here, the weight of the edges in the graph is mapped to the local field values of the LHZ. $J_{ij}$ demonstrates an individual node, while C1, C2, and C3 are penalty terms. The two nodes at the bottom always have a fixed value of one.
  • Figure 3: Circuit implementation with ideal parameters, (a) parametric oscillators with anti-ferro interaction, here $L=159.15pH$, $C=159.15pF$, $R_n=200\Omega$ and diodes are 1N4148, the pump is applied to the capacitor's charge (b) Ancillary circuit is demonstrated. Here, the $R_{na}=46\Omega$, and the pump amplitude is twice the node values.
  • Figure 4: A tile implemented with the ideal nodes. Three connections are needed to get the correct ground states expected from the LHZ tile. Here, the connection between nodes is $200\Omega$, between ancilla and nodes $250\Omega$, and inside ancilla is $46\Omega$. The tile is repeated in the LHZ IM, and all the tiles are similar.
  • Figure 5: Simulation results of 1000 runs for a single tile and 4-node LHZ network, (a) tile simulation results show the high probability of even states, (b) 4-node LHZ network simulation results for an unweighted Max-Cut network. The correct results are two ones and two zeros. By shifting the annealing time, we can get different correct answers.
  • ...and 3 more figures