Cryogenic Control and Readout Integrated Circuits for Solid-State Quantum Computing

Abstract

In the pursuit of quantum computing, solid-state quantum systems, particularly superconducting ones, have made remarkable advancements over the past two decades. However, achieving fault-tolerant quantum computing for next-generation applications necessitates the integration of several million qubits, which presents significant challenges in terms of interconnection complexity and latency that are currently unsolvable with state-of-the-art room-temperature control and readout electronics. Recently, cryogenic integrated circuits (ICs), including CMOS radio-frequency ICs and rapid-single-flux-quantum-logic ICs, have emerged as potential alternatives to room-temperature electronics. Unlike their room-temperature counterparts, these ICs are deployed within cryostats to enhance scalability by reducing the number and length of transmission lines. Additionally, operating at cryogenic temperatures can suppress electronic noise and improve qubit control fidelity. However, for CMOS ICs specifically, circuit design uncertainties arise due to a lack of reliable models for cryogenic field effect transistors as well as issues related to severe fickle noises and power dissipation at cryogenic temperatures. This paper provides a comprehensive review of recent research on both types of cryogenic control and readout ICs but primarily focuses on the more mature CMOS technology. The discussion encompasses principles underlying control and readout techniques employed in cryogenic CMOS ICs along with their architectural designs; characterization and modeling approaches for field effect transistors under cryogenic conditions; as well as fundamental concepts pertaining to rapid single flux quantum circuits.

Figures (9)

• Figure 1: Control principle and structure of qubits. (a) Structure of Loss-Divincenzo spin qubit. (b) Structure of transmons, the one with fixed frequency on the left, the one with tunable frequency on the right. (c) Effect of microwave pulse on Bloch sphere (d). Level structure of transmon. (e) Time domain diagram of envelopes. (Their integral values over $\mathbb{R}$ are set to 1. The width of finite-length envelopes $T=3\sigma$ for Gauss envelope, where $\sigma$ is the standard deviation of Gauss envelope. The second zero point of the raised cosine envelope is set to $T/2$) (f) Frequency domain diagram of envelopes. Panel (a) is from Ref. Burkard_Rev_Mod_Phys_2023
• Figure 2: RT C/R electronics. (a) Direct conversion transmitter for QPSK. (b) Sliding intermediate frequency receiver. (c) System structure of RT C/R electronics. (d) 1 dB gain compression point. (e) 3rd order intermodulation point. (f) IRR, LORR, and SFDR.
• Figure 3: Proposed System Structure of Cryo-CMOS ICs. Figure is from Ref. Charbon_ISSCC_2017.
• Figure 4: Structure, models, and band structure of MOSFET. (a) Geometric structures of FETs. (b) Simplest small signal model. (c) Band structure of MOSFET at cryogenic temperature. (Where the y-axis represents the depth into the substrate) (d) Small signal model of FDSOI MOSFET. Panel (c) is from Ref. BeckersTED2018, panel (d) is from Ref. HanESSDERC2022.
• Figure 5: System structures of modulator prototypes. (a) System structure of Google's works. (chip#1,2 corresponds to BardinISSCC2019YooISSCC2023 separately.) (b) Interconnection relation of the digital part and DACs in BardinISSCC2019. (c) System structure and schematic of DAC in KangISSCC2023KangISSCC2022KangVLSI2021. (d) System architecture of IBM's work FrankISSCC2022. (e) Chip in Reference ParkJSSC2021. (f) Gate-level structure in FrankISSCC2022. (g) Chip in Reference GuoISSCC2023. Panel (a) is from Refs. BardinISSCC2019YooISSCC2023, (b) is from Ref. BardinISSCC2019, (c) is from Refs. KangISSCC2023KangISSCC2022KangVLSI2021, (e) is from Ref. ParkJSSC2021, (f) is from Ref. FrankISSCC2022, (g) is from Ref. GuoISSCC2023.