TEXEL: A neuromorphic processor with on-chip learning for beyond-CMOS device integration

TL;DR

TEXEL serves as an accessible platform to bridge the gap between CMOS-based neuromorphic computation and the latest advancements in emerging devices, and provides a practical system for testing bio-inspired learning algorithms alongside emerging devices.

Abstract

Recent advances in memory technologies, devices and materials have shown great potential for integration into neuromorphic electronic systems. However, a significant gap remains between the development of these materials and the realization of large-scale, fully functional systems. One key challenge is determining which devices and materials are best suited for specific functions and how they can be paired with CMOS circuitry. To address this, we introduce TEXEL, a mixed-signal neuromorphic architecture designed to explore the integration of on-chip learning circuits and novel two- and three-terminal devices. TEXEL serves as an accessible platform to bridge the gap between CMOS-based neuromorphic computation and the latest advancements in emerging devices. In this paper, we demonstrate the readiness of TEXEL for device integration through comprehensive chip measurements and simulations. TEXEL provides a practical system for testing bio-inspired learning algorithms alongside emerging devices, establishing a tangible link between brain-inspired computation and cutting-edge device research.

Figures (11)

• Figure 1: The fabricated TEXEL chip.a) Footprint of the chip, indicating the location of the architectural blocks. b) The neuron block footprint, indicating the synaptic fan-in of the soma within the block. The location of the plastic and non-plastic synapses are shown with excitatory (exc) and inhibitory (inh) types. The plastic synapses contain the contacts and interface circuitry for BEOL integration of memristive devices. c) A photograph of the 9$\times$7,5 die, fabricated using the XFAB 180 process.
• Figure 2: Measurements of the neuron circuitry on the TEXEL chip.a) The measured firing rates of all neurons on TEXEL in response to a constant input current. b) Measurement of the membrane potential of a single neuron in response to a step input. The neuron's adaptation characteristic is evident as its firing rate begins high and gradually diminishes to attain a steady state. c) Measurements of the variations in the instantaneous firing rate and timing of output spikes in relation to the magnitude of injected into the soma. d) The recorded membrane potential response of a neuron receiving presynaptic Poisson input at the static excitatory synapses. Below, in blue, is the presynaptic spike train, while above, in green, the postsynaptic spikes indicate the neuron's spiking activity.
• Figure 3: Silicon measurements of a single plastic synapse and its neuron, demonstrating local synaptic plasticity (complementary to Fig. \ref{['fig:texel_soma_synapse_circuits']}b).a) A presynaptic spike train induces a current (blue) read by the , while simultaneous stimulation with an triggers postsynaptic spiking (green). Shaded regions indicate when the post-trace exceeds the lower threshold, reflecting short-term memory. The $\mathrm{Ca}^{2+}$ trace (orange) accumulates postsynaptic activity, showing plasticity when above its threshold. b) measurements assess the impact pre- and postsynaptic spike timing, $\Delta t = \mathrm{pre} - \mathrm{post}$, on the analog weight of the synapse ($w$). c) This curve demonstrates modulation of potentiation and depression through analog biasing. d) results show the probability of the synapse having high or low weight based on pre- and postsynaptic firing rates ($\nu_{\text{pre}}$ and $\nu_{\text{post}}$).
• Figure 4: Spectre post-layout simulations of the read protocol for the differential normalizer synapse on TEXEL.a) A read pulse with a width of 500 s activates the normalizer circuit, sourcing $I_{\mathrm{neg}}$ and $I_{\mathrm{pos}}$. The circuit outputs a non-zero current, $I_{\mathrm{norm}}$, if $I_{\mathrm{pos}} > I_{\mathrm{neg}}$, which is integrated by a synapse, resulting in a current $I_{\mathrm{syn}}$ sent to the neuron. The left panel shows high weight storage ($\mathrm{R}_{\mathrm{pos}} < \mathrm{R}_{\mathrm{neg}}$), eliciting a response, while the right panel shows low weight storage ($\mathrm{R}_{\mathrm{neg}} < \mathrm{R}_{\mathrm{pos}}$), where no current is integrated. b) With $R_{\text{pos}}=\qty{1}{\giga \ohm}$, device capacitance of $C=\qty{100}{\fF}$, and a read pulse width of 500, the relative resistances of both devices are varied by sweeping $R_{\text{neg}}$. The average output current of the normalizer circuit is measured as a % of $\mathrm{norm\_bias}$, showing non-zero current when the positive device's conductance exceeds that of the negative device. c) Simulations explore device characteristics' impact on compatibility with TEXEL. The cross ($\times$) represents a device with $C = \qty{100}{\fF}$, $\mathrm{G}_\mathrm{on} / \mathrm{G}_\mathrm{off}=100$, $\mathrm{R}_{\text{on}} = \qty{1}{\giga \ohm}$, and a read pulse width of 500. Heatmaps indicate average current from the normalizer as a percentage of $\mathrm{norm\_bias}$. d) A sweep of the device's capacitance versus its on/off ratio is shown with $\mathrm{R}_{\text{on}}$ fixed at 1.
• Figure 5: Dynamic and static power measurements of the TEXEL chip, focusing on energy consumption for synaptic operations and neuron spikes.a) Dynamic power consumption versus postsynaptic event rate, measured for the three isolated power supplies. b) Energy per spike for increasing mean firing rates across each power supply. c) Dynamic power consumption of the analog power supply against postsynaptic event rate. d) Energy consumed per spike versus mean firing rate per neuron, for the analog power supply. e) Dynamic power consumption during random synaptic stimulation at increasing input event rates. f) Energy consumption per synaptic operation against input event rate. g) Breakdown of static power consumption while neurons are inactive and synapses are unstimulated.