LLC Intra-set Write Balancing

TL;DR

This work proposes a sample-based blocking technique for the Last Level Cache (LLC) that significantly balances write traffic to the cache and improves the overall lifespan of the memory cells while having better performance to the base-line system.

Abstract

The increasing use of Non-Volatile Memory (NVM) in computer architecture has brought about new challenges, one of which is the write endurance problem. Frequent writes to a particular cache cell in NVM can lead to degradation of the memory cell and reduce its lifespan. To solve this problem, we propose a sample-based blocking technique for the Last Level Cache (LLC). Our approach involves defining a threshold value and sampling a subset of cache sets. If the number of writes to a way in a sampled set exceeds the threshold, the way is blocked, and writes are redirected to other ways. We also maintain a history structure to record the number of writes in a set and a PC-Table to use for blocking in unsampled sets. Based on blocking on sampled sets, variance of values stored in history is used to determine whether blocking had a positive impact or not, and on this basis, value corresponding to instruction pointer is incremented or decremented. This value is later used for blocking in unsampled sets. Our results show that our approach significantly balances write traffic to the cache and improves the overall lifespan of the memory cells while having better performance to the base-line system. Our approach can also be applied to other cache hierarchies and NVM technologies to mitigate the problem of write endurance.

Figures (7)

• Figure 1: Structure of counter used to record number of writes in I cycles and the instruction pointer that caused the write
• Figure 2: Structure of history which stores past 'k' counter values for each set. For implementation of algorithm, k = 8 is taken.
• Figure 3: Schematic diagram of flow of the algorithm. Some sets are sampled as sample sets, and for them counter values are calculated and stored in history after every 'I' cycles. At the end of each of the interval of 'I' cycles, PC-table is trained based on whether blocking due to an instruction pointer had positive effect or not. For unsampled sets, whenever a write occurs, the instruction pointer is used to access the PC-table and get the value. If value < 0, then that way is blocked for write operations, else normal write can occur.
• Figure 4: Graph of counter values vs ways. It depicts how blocking using equal writes or other similar approaches can lead to an oscillatory nature.
• Figure 5: Graph of number of accesses vs instruction pointers for sampled sets and not sampled sets. We can observe that some sets instruction pointers have large accesses and others very less.