Simulation of Quantum Computers: Review and Acceleration Opportunities

TL;DR

The paper surveys the landscape of classical simulation of quantum computers, emphasizing the exponential resource demands of simulating large quantum systems and the need for hardware-aware acceleration. It categorizes simulation approaches into device, gate, and algorithmic levels, and then analyzes acceleration strategies across CPU, GPU, and FPGA platforms, including Schrödinger-style, Feynman-style, and tensor-network methods. Key contributions include a structured taxonomy of simulation tools, a synthesis of optimization techniques (data compression, precision control, memory locality, and circuit clustering), and insights into future hardware directions such as hybrid CPU-QPU setups and FPGA-optimized kernels. The work highlights practical guidelines for achieving scalable quantum circuit simulations and identifies promising directions to push the size and speed of simulations in the coming years, with implications for algorithm development, hardware design, and benchmarking.

Abstract

Quantum computing has the potential to revolutionize multiple fields by solving complex problems that can not be solved in reasonable time with current classical computers. Nevertheless, the development of quantum computers is still in its early stages and the available systems have still very limited resources. As such, currently, the most practical way to develop and test quantum algorithms is to use classical simulators of quantum computers. In addition, the development of new quantum computers and their components also depends on simulations. Given the characteristics of a quantum computer, their simulation is a very demanding application in terms of both computation and memory. As such, simulations do not scale well in current classical systems. Thus different optimization and approximation techniques need to be applied at different levels. This review provides an overview of the components of a quantum computer, the levels at which these components and the whole quantum computer can be simulated, and an in-depth analysis of different state-of-the-art acceleration approaches. Besides the optimizations that can be performed at the algorithmic level, this review presents the most promising hardware-aware optimizations and future directions that can be explored for improving the performance and scalability of the simulations.

Figures (10)

• Figure 1: Bloch-sphere representation of a qubit.
• Figure 2: A single-qubit circuit, which applies the Pauli gates X, Y, and Z in succession.
• Figure 3: A two-qubit circuit, which executes a Pauli X gate on the first qubit and a Pauli Y gate on the second qubit
• Figure 4: (a) Example of order-3 tensor, (b) An order-k tensor requires k-indices to be accessed.
• Figure 5: The tensors D and E are contracted into a single tensor F, with indices i and k.