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Using Intermittent Chaotic Clocks to Secure Cryptographic Chips

Abdollah Masoud Darya, Sohaib Majzoub, Ali A. El-Moursy, Mohamed Wed Eladham, Khalid Javeed, Ahmed S. Elwakil

TL;DR

All proposed chaotic clocking schemes successfully protect the driven chip against attacks, with the clocks produced by the optimized Ikeda, Henon, and logistic maps achieving the lowest-timing overhead.

Abstract

This letter proposes using intermittent chaotic clocks, generated from chaotic maps, to drive cryptographic chips running the Advanced Encryption Standard as a countermeasure against Correlation Power Analysis attacks. Five different chaotic maps -- namely: the Logistic map, the Bernoulli shift map, the Henon map, the Tent map, and the Ikeda map -- are used in this work to generate chaotic clocks. The performance of these chaotic clocks is evaluated in terms of timing overhead and the resilience of the driven chip against Correlation Power Analysis attacks. All proposed chaotic clocking schemes successfully protect the driven chip against attacks, with the clocks produced by the optimized Ikeda, Henon, and Logistic maps achieving the lowest timing overhead. These optimized maps, due to their intermittent chaotic behavior, exhibit lower timing overhead compared to previous work. Notably, the chaotic clock generated by the optimized Ikeda map approaches the theoretical limit of timing overhead, i.e., half the execution time of a reference periodic clock.

Using Intermittent Chaotic Clocks to Secure Cryptographic Chips

TL;DR

All proposed chaotic clocking schemes successfully protect the driven chip against attacks, with the clocks produced by the optimized Ikeda, Henon, and logistic maps achieving the lowest-timing overhead.

Abstract

This letter proposes using intermittent chaotic clocks, generated from chaotic maps, to drive cryptographic chips running the Advanced Encryption Standard as a countermeasure against Correlation Power Analysis attacks. Five different chaotic maps -- namely: the Logistic map, the Bernoulli shift map, the Henon map, the Tent map, and the Ikeda map -- are used in this work to generate chaotic clocks. The performance of these chaotic clocks is evaluated in terms of timing overhead and the resilience of the driven chip against Correlation Power Analysis attacks. All proposed chaotic clocking schemes successfully protect the driven chip against attacks, with the clocks produced by the optimized Ikeda, Henon, and Logistic maps achieving the lowest timing overhead. These optimized maps, due to their intermittent chaotic behavior, exhibit lower timing overhead compared to previous work. Notably, the chaotic clock generated by the optimized Ikeda map approaches the theoretical limit of timing overhead, i.e., half the execution time of a reference periodic clock.

Paper Structure

This paper contains 13 sections, 6 equations, 4 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Chaotic Maps
  3. The Logistic Map
  4. The Bernoulli Shift Map
  5. The Tent Map
  6. The Henon Map
  7. The Ikeda Map
  8. Results and Discussion
  9. Parameter Tuning
  10. CPA Analysis
  11. Experimental Setup
  12. Discussion
  13. Conclusion

Figures (4)

  • Figure 1: Search of optimal $B$ which (i) maintains chaotic behavior (upper trace) and (ii) maximizes the chaotic clock ratio (lower trace). The optimal $B$ of the Ikeda map is represented by the dashed line.
  • Figure 2: Results of the CPA attacks on the AES chip driven by different clocks: (a) unprotected periodic clock, (b) Logistic map chaotic clock, (c) Bernoulli shift map chaotic clock, (d) Henon map chaotic clock, (e) Tent map chaotic clock, and (f) Ikeda map chaotic clock.
  • Figure 3: Experimental Ikeda map ($B=0.6656$) compared to the simulated Ikeda map ($B=0.6645$) for $3\times10^4$ samples.
  • Figure 4: Samples of the experimental chaotic clock of the Ikeda map (top left trace) and a periodic clock (lower left trace) from the DE2 board. Right plot: statistical distribution of the experimental clock periods of the Ikeda map using $10^6$ samples from the DE2.