Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Characterizing and Optimizing Real-Time Optimal Control for Embedded SoCs

Kris Shengjun Dong, Dima Nikiforov, Widyadewi Soedarmadji, Minh Nguyen, Vikram Jain, Christopher W. Fletcher, Yakun Sophia Shao

TL;DR

The paper tackles the challenge of running real-time model predictive control (MPC) on resource-constrained embedded SoCs by performing a rigorous design-space exploration across scalar RISC-V CPUs, RVV-enabled vector cores, and Gemmini-style systolic accelerators. It pairs kernel-level optimizations (loop unrolling, operator fusion, static scheduling, scratchpad data flow) with a code-generation flow (matlib) to automate fused, tiled implementations, achieving up to $3.71\times$ speedups and up to $27\%$ system-power reductions in end-to-end robotic tasks. Hardware-in-the-loop validation on a fabricated Cygnus RVV SoC with a CrazyFlie drone demonstrates real-time MPC viability and shows how architecture choice interacts with workload characteristics and SWaP constraints. The work provides concrete design guidance and tooling for deploying real-time robot control on heterogeneous embedded SoCs, highlighting the substantial gains from software-centric optimizations and the resulting reduction in engineering overhead via code generation.

Abstract

Resource-limited robots face significant challenges in executing computationally intensive tasks, such as locomotion and manipulation, particularly for real-time optimal control algorithms like Model Predictive Control (MPC). This paper provides a comprehensive design space exploration to identify optimal hardware computation architectures for these demanding model-based control algorithms. We profile and optimize representative architectural designs, including general-purpose scalar CPUs, vector processors, and specialized accelerators. By characterizing kernel-level benchmarks and end-to-end robotic scenarios, including a hardware-in-the-loop evaluation on a fabricated RISC-V multi-core vector SoC, we present a quantitative comparison of performance, area, and utilization across distinct architectural design points. Our findings demonstrate that targeted architectural modifications, coupled with deep software and system optimizations, enable up to 3.71x speedups for MPC, resulting in up to 27% system-level power reductions while completing robotic tasks. Finally, we propose a code generation flow designed to simplify the complex engineering effort required for mapping robotic workloads onto specialized architectures.

Characterizing and Optimizing Real-Time Optimal Control for Embedded SoCs

TL;DR

The paper tackles the challenge of running real-time model predictive control (MPC) on resource-constrained embedded SoCs by performing a rigorous design-space exploration across scalar RISC-V CPUs, RVV-enabled vector cores, and Gemmini-style systolic accelerators. It pairs kernel-level optimizations (loop unrolling, operator fusion, static scheduling, scratchpad data flow) with a code-generation flow (matlib) to automate fused, tiled implementations, achieving up to speedups and up to system-power reductions in end-to-end robotic tasks. Hardware-in-the-loop validation on a fabricated Cygnus RVV SoC with a CrazyFlie drone demonstrates real-time MPC viability and shows how architecture choice interacts with workload characteristics and SWaP constraints. The work provides concrete design guidance and tooling for deploying real-time robot control on heterogeneous embedded SoCs, highlighting the substantial gains from software-centric optimizations and the resulting reduction in engineering overhead via code generation.

Abstract

Resource-limited robots face significant challenges in executing computationally intensive tasks, such as locomotion and manipulation, particularly for real-time optimal control algorithms like Model Predictive Control (MPC). This paper provides a comprehensive design space exploration to identify optimal hardware computation architectures for these demanding model-based control algorithms. We profile and optimize representative architectural designs, including general-purpose scalar CPUs, vector processors, and specialized accelerators. By characterizing kernel-level benchmarks and end-to-end robotic scenarios, including a hardware-in-the-loop evaluation on a fabricated RISC-V multi-core vector SoC, we present a quantitative comparison of performance, area, and utilization across distinct architectural design points. Our findings demonstrate that targeted architectural modifications, coupled with deep software and system optimizations, enable up to 3.71x speedups for MPC, resulting in up to 27% system-level power reductions while completing robotic tasks. Finally, we propose a code generation flow designed to simplify the complex engineering effort required for mapping robotic workloads onto specialized architectures.

Paper Structure

This paper contains 58 sections, 4 equations, 19 figures, 1 table, 3 algorithms.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Characterization and Benchmarking
  4. Architectural Design Points in Robotics
  5. Workload Overview
  6. Workload Structure
  7. Programming Interface and Libraries
  8. Characterization and Optimization
  9. Optimizations for Vector Cores
  10. Hardware and Software Loop Unrolling
  11. Operator Fusion
  12. Optimizations for Systolic Arrays
  13. Static Scheduling of Gemmini Kernels
  14. Reduction of Redundant Configuration Operations
  15. Use of Gemmini's Fine-Grained ISA
  16. ...and 43 more sections

Figures (19)

  • Figure 1: FLOP Breakdown of TinyMPC Kernels
  • Figure 2: Categories of Target Hardware Architectures to be Profiled and Evaluated: CPU, tightly integrated accelerators, and decoupled co-processors.
  • Figure 3: Out-of-box application of matlib vs hand-optimized vectorized TinyMPC
  • Figure 4: Performance of TinyMPC using Saturn with varying sizes of LMUL
  • Figure 5: Library vs Fused-Operator Speedup on Rocket-driven 512V256D Saturn
  • ...and 14 more figures