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Efficiera Residual Networks: Hardware-Friendly Fully Binary Weight with 2-bit Activation Model Achieves Practical ImageNet Accuracy

Shuntaro Takahashi, Takuya Wakisaka, Hiroyuki Tokunaga

TL;DR

This work introduces Efficiera Residual Networks (ERNs), a model optimized for low-resource edge devices that achieves full ultra-low-bit quantization, with all weights, including the initial and output layers, being binary, and activations set at 2 bits.

Abstract

The edge-device environment imposes severe resource limitations, encompassing computation costs, hardware resource usage, and energy consumption for deploying deep neural network models. Ultra-low-bit quantization and hardware accelerators have been explored as promising approaches to address these challenges. Ultra-low-bit quantization significantly reduces the model size and the computational cost. Despite progress so far, many competitive ultra-low-bit models still partially rely on float or non-ultra-low-bit quantized computation such as the input and output layer. We introduce Efficiera Residual Networks (ERNs), a model optimized for low-resource edge devices. ERNs achieve full ultra-low-bit quantization, with all weights, including the initial and output layers, being binary, and activations set at 2 bits. We introduce the shared constant scaling factor technique to enable integer-valued computation in residual connections, allowing our model to operate without float values until the final convolution layer. Demonstrating competitiveness, ERNs achieve an ImageNet top-1 accuracy of 72.5pt with a ResNet50-compatible architecture and 63.6pt with a model size less than 1MB. Moreover, ERNs exhibit impressive inference times, reaching 300FPS with the smallest model and 60FPS with the largest model on a cost-efficient FPGA device.

Efficiera Residual Networks: Hardware-Friendly Fully Binary Weight with 2-bit Activation Model Achieves Practical ImageNet Accuracy

TL;DR

This work introduces Efficiera Residual Networks (ERNs), a model optimized for low-resource edge devices that achieves full ultra-low-bit quantization, with all weights, including the initial and output layers, being binary, and activations set at 2 bits.

Abstract

The edge-device environment imposes severe resource limitations, encompassing computation costs, hardware resource usage, and energy consumption for deploying deep neural network models. Ultra-low-bit quantization and hardware accelerators have been explored as promising approaches to address these challenges. Ultra-low-bit quantization significantly reduces the model size and the computational cost. Despite progress so far, many competitive ultra-low-bit models still partially rely on float or non-ultra-low-bit quantized computation such as the input and output layer. We introduce Efficiera Residual Networks (ERNs), a model optimized for low-resource edge devices. ERNs achieve full ultra-low-bit quantization, with all weights, including the initial and output layers, being binary, and activations set at 2 bits. We introduce the shared constant scaling factor technique to enable integer-valued computation in residual connections, allowing our model to operate without float values until the final convolution layer. Demonstrating competitiveness, ERNs achieve an ImageNet top-1 accuracy of 72.5pt with a ResNet50-compatible architecture and 63.6pt with a model size less than 1MB. Moreover, ERNs exhibit impressive inference times, reaching 300FPS with the smallest model and 60FPS with the largest model on a cost-efficient FPGA device.

Paper Structure

This paper contains 17 sections, 7 equations, 3 figures, 7 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Low-bit quantization of neural networks
  4. Network Design Optimization for Computer Architectures
  5. Efficiera Residual Networks
  6. Ultra-low-bit quantization of CNNs
  7. Network Architecture Design with Minimal Operation Set
  8. Pixel Embedding Module: Generalized Thermometer Encoding
  9. Stem Module
  10. Integer-Valued Residual Connection
  11. Output Layer
  12. Experiment
  13. Experiment Settings
  14. Result
  15. Deployment to FPGA Device
  16. ...and 2 more sections

Figures (3)

  • Figure 1: Model Size and ImageNet Top-1 Accuracy of the ultra-low-bit quantized models. See also Section \ref{['sec:result']}.
  • Figure 2: Network architecture of ERNs. The values in the bracket are the output shape in (channel, height, width).
  • Figure 3: ConvBlock architecture for ERNs