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Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units

Maedeh Ghaderi, Arvin Delavari, Faraz Ghoreishy, Sattar Mirzakuchaki

TL;DR

This study proposes a hardware MLP neural network implemented in 45nm CMOS technology, in which MAC units of the neurons incorporate error and power controllable approximate multipliers for classification of the MNIST dataset.

Abstract

Multi-Layer Perceptrons (MLP) are powerful tools for representing complex, non-linear relationships, making them essential for diverse machine learning and AI applications. Efficient hardware implementation of MLPs can be achieved through many hardware and architectural design techniques. These networks excel at predictive modeling and classification tasks like image classification, making them a popular choice. Approximate computing techniques are increasingly used to optimize critical path delay, area, power, and overall hardware efficiency in high-performance computing systems through controlled error and related trade-offs. This study proposes a hardware MLP neural network implemented in 45nm CMOS technology, in which MAC units of the neurons incorporate error and power controllable approximate multipliers for classification of the MNIST dataset. The optimized network consists of 10 neurons within the hidden layers, occupying 0.026mm2 of area, with 5.55mW at 100MHz frequency in accurate mode and 4.81mW in lowest accuracy mode. The experiments indicate that the proposed design achieves a maximum rate of 13.33% decrease overall and 24.78% in each neuron's power consumption with only a 0.92% decrease in accuracy in comparison with accurate circuit.

Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units

TL;DR

This study proposes a hardware MLP neural network implemented in 45nm CMOS technology, in which MAC units of the neurons incorporate error and power controllable approximate multipliers for classification of the MNIST dataset.

Abstract

Multi-Layer Perceptrons (MLP) are powerful tools for representing complex, non-linear relationships, making them essential for diverse machine learning and AI applications. Efficient hardware implementation of MLPs can be achieved through many hardware and architectural design techniques. These networks excel at predictive modeling and classification tasks like image classification, making them a popular choice. Approximate computing techniques are increasingly used to optimize critical path delay, area, power, and overall hardware efficiency in high-performance computing systems through controlled error and related trade-offs. This study proposes a hardware MLP neural network implemented in 45nm CMOS technology, in which MAC units of the neurons incorporate error and power controllable approximate multipliers for classification of the MNIST dataset. The optimized network consists of 10 neurons within the hidden layers, occupying 0.026mm2 of area, with 5.55mW at 100MHz frequency in accurate mode and 4.81mW in lowest accuracy mode. The experiments indicate that the proposed design achieves a maximum rate of 13.33% decrease overall and 24.78% in each neuron's power consumption with only a 0.92% decrease in accuracy in comparison with accurate circuit.

Paper Structure

This paper contains 9 sections, 2 equations, 7 figures, 1 table.

Table of Contents

  1. Introduction
  2. Related Works
  3. Proposed Neural Networks’s Architecture
  4. Error Controllable MAC Unit structure
  5. Neurons’ structure
  6. Datapath and overall structure
  7. Controller
  8. Experimental Results
  9. Conclusion

Figures (7)

  • Figure 1: Proposed fully connected MLP neural network ($B_{layer}$ are for Bias factors and $W_{layer}$ are for Weights).
  • Figure 2: Proposed MAC unit with error controllable approximate multiplier circuit
  • Figure 3: Structure of neuron module in the proposed MLP neural network with error controllable MAC units
  • Figure 4: Datapath of the implemented MLP neural network
  • Figure 5: Improvements in overall power consumption all 32 dynamic configurations of MAC units (neurons)
  • ...and 2 more figures