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Reducing Data Bottlenecks in Distributed, Heterogeneous Neural Networks

Ruhai Lin, Rui-Jie Zhu, Jason K. Eshraghian

TL;DR

The paper tackles data movement bottlenecks in distributed, heterogeneous neural networks on embedded hardware. It introduces bottleneck layers that replace time-multiplexed data paths with learnable embeddings to reduce inter-chip IO, enabling time-sharing of signals. Through CIFAR100 software experiments, it shows that increasing bottleneck ratios generally lowers accuracy, with shallower models more sensitive, while hardware measurements confirm substantial reductions in data transfer. The work provides a practical framework for co-designing neural networks and hardware to achieve favorable trade-offs between performance and data movement in resource-constrained environments.

Abstract

The rapid advancement of embedded multicore and many-core systems has revolutionized computing, enabling the development of high-performance, energy-efficient solutions for a wide range of applications. As models scale up in size, data movement is increasingly the bottleneck to performance. This movement of data can exist between processor and memory, or between cores and chips. This paper investigates the impact of bottleneck size, in terms of inter-chip data traffic, on the performance of deep learning models in embedded multicore and many-core systems. We conduct a systematic analysis of the relationship between bottleneck size, computational resource utilization, and model accuracy. We apply a hardware-software co-design methodology where data bottlenecks are replaced with extremely narrow layers to reduce the amount of data traffic. In effect, time-multiplexing of signals is replaced by learnable embeddings that reduce the demands on chip IOs. Our experiments on the CIFAR100 dataset demonstrate that the classification accuracy generally decreases as the bottleneck ratio increases, with shallower models experiencing a more significant drop compared to deeper models. Hardware-side evaluation reveals that higher bottleneck ratios lead to substantial reductions in data transfer volume across the layers of the neural network. Through this research, we can determine the trade-off between data transfer volume and model performance, enabling the identification of a balanced point that achieves good performance while minimizing data transfer volume. This characteristic allows for the development of efficient models that are well-suited for resource-constrained environments.

Reducing Data Bottlenecks in Distributed, Heterogeneous Neural Networks

TL;DR

The paper tackles data movement bottlenecks in distributed, heterogeneous neural networks on embedded hardware. It introduces bottleneck layers that replace time-multiplexed data paths with learnable embeddings to reduce inter-chip IO, enabling time-sharing of signals. Through CIFAR100 software experiments, it shows that increasing bottleneck ratios generally lowers accuracy, with shallower models more sensitive, while hardware measurements confirm substantial reductions in data transfer. The work provides a practical framework for co-designing neural networks and hardware to achieve favorable trade-offs between performance and data movement in resource-constrained environments.

Abstract

The rapid advancement of embedded multicore and many-core systems has revolutionized computing, enabling the development of high-performance, energy-efficient solutions for a wide range of applications. As models scale up in size, data movement is increasingly the bottleneck to performance. This movement of data can exist between processor and memory, or between cores and chips. This paper investigates the impact of bottleneck size, in terms of inter-chip data traffic, on the performance of deep learning models in embedded multicore and many-core systems. We conduct a systematic analysis of the relationship between bottleneck size, computational resource utilization, and model accuracy. We apply a hardware-software co-design methodology where data bottlenecks are replaced with extremely narrow layers to reduce the amount of data traffic. In effect, time-multiplexing of signals is replaced by learnable embeddings that reduce the demands on chip IOs. Our experiments on the CIFAR100 dataset demonstrate that the classification accuracy generally decreases as the bottleneck ratio increases, with shallower models experiencing a more significant drop compared to deeper models. Hardware-side evaluation reveals that higher bottleneck ratios lead to substantial reductions in data transfer volume across the layers of the neural network. Through this research, we can determine the trade-off between data transfer volume and model performance, enabling the identification of a balanced point that achieves good performance while minimizing data transfer volume. This characteristic allows for the development of efficient models that are well-suited for resource-constrained environments.

Paper Structure

This paper contains 23 sections, 5 equations, 3 figures.

Table of Contents

  1. Introduction
  2. Related Work
  3. Bottleneck Architectures in Neural Networks
  4. Hardware-aware Neural Network Design
  5. Efficient Neural Network Design
  6. Methods
  7. Layers of Neural Network
  8. Input Layer
  9. Weights and Biases
  10. Linear Transformation
  11. Activation Function
  12. Output Layer
  13. Bottleneck
  14. Bottleneck in ResNet
  15. Experiments
  16. ...and 8 more sections

Figures (3)

  • Figure 1: Illustration of an artificial neuron with ReLU activation and the bottleneck structure in a multi-chip module (MCM) architecture. The bottleneck reduces inter-chip communication overhead between System A and System B.
  • Figure 2: Accuracy vs Bottleneck for Different ResNet Architectures.
  • Figure 3: Data Transferred vs Layer Number for Different Bottleneck Ratio.