Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning

TL;DR

This paper proposes a new SRAM-based Compute-In-Memory (CIM) accelerator optimized for Spiking Neural Networks (SNNs) Inference with a multiport SRAM design with multiple decoupled Read ports to enhance the throughput and Transposable Read-Write ports to facilitate online learning.

Abstract

Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones, wearables, and Internet-of-Things sensor systems. In this paper, we propose a new SRAM-based Compute-In-Memory (CIM) accelerator optimized for Spiking Neural Networks (SNNs) Inference. Our proposed architecture employs a multiport SRAM design with multiple decoupled Read ports to enhance the throughput and Transposable Read-Write ports to facilitate online learning. Furthermore, we develop an Arbiter circuit for efficient data-processing and port allocations during the computation. Results for a 128$\times$128 array in 3nm FinFET technology demonstrate a 3.1$\times$ improvement in speed and a 2.2$\times$ enhancement in energy efficiency with our proposed multiport SRAM design compared to the traditional single-port design. At system-level, a throughput of 44 MInf/s at 607 pJ/Inf and 29mW is achieved.

Figures (7)

• Figure 1: Illustration of working principle of Spiking Neural Network, mapping to memory crossbar and traditional row-wise SRAM access versus Transposable column-wise SRAM access.
• Figure 2: Overview of proposed Macro Architecture. Green indicates the Transposed Read/Write access, with the Inference Read access in Purple.
• Figure 3: Schematic and layout of proposed five-Read and one-Write (1RW+4R) SRAM Cell.
• Figure 4: The proposed logic-based 4-Port Arbiter based on four cascaded 1-Port Arbiters.
• Figure 5: Proposed Neuron for ESAM Architecture.