Heracles: A HfO2 Ferroelectric Capacitor Compact Model for Efficient Circuit Simulations

TL;DR

The paper addresses the lack of comprehensive, physics-based compact models for HfO2-based ferroelectric capacitors by introducing Heracles, a VerilogA SPICE model for HZO FeCaps that partitions the device into ferroelectric, interface, and depletion regions with a non-equilibrium switching dynamics and depolarization feedback. It integrates parasitics, leakage mechanisms, thermal effects, and device-to-device variability to enable reliable Monte Carlo DTCO analyses and scalable array simulations. The model is calibrated against experimental wake-up data and validated through extensive comparisons of hysteresis, switching kinetics, and capacitance behavior, including temperature effects. Demonstrations in current-programming circuits and large arrays show practical convergence times and the potential for FeCap-based memory and analog computing design, with open-source availability under MIT license and a path toward FeFET extensions.

Abstract

The growing use of ferroelectric-based technology, extending beyond conventional memory storage applications, necessitates the development of compact models that can be easily integrated into circuit simulation environments. These models assist circuit designers in the design and the early assessment of the performance of their systems. The Heracles model is a physics-based compact model for circuit simulations in a SPICE environment for HfO2-based ferroelectric capacitors (FeCaps). The model has been calibrated based on experimental data obtained from HfO2-based FeCaps. A thermal model with an accurate description of the device parasitics is included to derive precise device characteristics based on first principles. The incorporation of statistical device data enables Monte Carlo analysis based on realistic distributions, thereby rendering the model particularly well-suited for design-technology co-optimization (DTCO). The model's efficacy is further demonstrated in circuit simulations using an integrated circuit with current programming, wherein partial switching of the ferroelectric polarization is observed. Finally, the model was benchmarked in an array simulation, reaching convergence in 1.8 s with an array size of 100 kb.

Figures (6)

• Figure 1: (a) Equivalent circuit of the model, with internal nodes for the interface and depletion layers. The voltage applied to the device is then distributed between the branches by the SPICE simulation. (b) Illustration of the energy profile based on Landau theory, where the ferroelectric switching process is modeled by a thermodynamic transition over the barrier $W_b$, modulated by the applied field (purple curve).
• Figure 2: (a) Simulated small signal capacitance $C_{depl}$, a part of the total MFM capacitance (cf. Fig. \ref{['fig:3']}(d)), for different carrier densities in the depletion layer. A hysteresis is observed due to the the independent modeling of the depletion layers for each polarization direction. (b) Simulated polarization hysteresis at 1 kHz for decreasing carrier densities in the depletion layer, where both the remanent polarization as well as the switching peak sharpness decrease as the carrier density in the electrode decreases. The dotted lines show the respective displacement currents.
• Figure 3: (a) Material stack of the metal-ferroelectric-metal (MFM) device from which the experimental data was gathered. (b) Hysteresis loop at 1 kHz for a woken-up device, resulting from the same parameters, showing that model generalizes the switching process well. (c) Simulated switching kinetics of the device and experimental data used for the parameter extraction. (d) Capacitance hysteresis of the whole device stack, simulated for a 100 kHz, 30 mV RMS sine.
• Figure 4: (a) Hysteresis at low voltages and 1 kHz frequency that do not saturate the polarization and have a lower apparent coercive field due to the increased voltage ramp rate. (b) Hysteresis of a pristine device for different voltages, obtained by adjusting $N_{depl}$ to 7$\cdot$10$\mathrm{^{21}}$ cm$^{-3}$, highlighting the increase of carrier density at the electrode interface as a possible contribution to the wake-up mechanism.
• Figure 5: (a) Variability of the polarization switching kinetics at 21 °C in the experiment and in the Monte Carlo simulation. (b) Switched polarization at 85 °C, due to the elevated temperatures the polarization screening was modeled by a decrease in $d_e$ and an increase in $Q_{fix,depl}$ to account for increased charge trapping.