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Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core

Arvin Delavari, Faraz Ghoreishy, Hadi Shahriar Shahhoseini, Sattar Mirzakuchaki

TL;DR

This work tackles energy efficiency in energy-constrained embedded systems through dynamic hardware approximation in a RISC-V core. It implements CSR-controlled, per-execution-unit approximate arithmetic (adder and multiplier) and a hierarchical 32×32 multiplier, evaluating post-synthesis metrics at 45nm and 500MHz. The study reports an average run-time energy efficiency improvement of about 9.21% and specific stage- and operation-level power reductions, demonstrating the practicality of hardware-accelerated approximation for embedded workloads. The findings highlight the potential of programmable approximation to tighten the accuracy-power trade-off in modern embedded processors, with avenues for broader architectural integration and real-time energy management.

Abstract

The limited energy available in most embedded systems poses a significant challenge in enhancing the performance of embedded processors and microcontrollers. One promising approach to address this challenge is the use of approximate computing, which can be implemented in both hardware and software layers to balance the trade-off between performance and power consumption. In this study, the impact of dynamic hardware approximation methods on the run-time energy efficiency of a RISC-V embedded processor with specialized features for approximate computing is investigated. The results indicate that the platform achieves an average energy efficiency of 13.3 pJ/instruction at a 500MHz clock frequency adhering approximation in 45nm CMOS technology. Compared to accurate circuits and computation, the approximate computing techniques in the processing core resulted in a significant improvement of 9.21% in overall energy efficiency, 60.83% in multiplication instructions, 14.64% in execution stage, and 9.23% in overall power consumption.

Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core

TL;DR

This work tackles energy efficiency in energy-constrained embedded systems through dynamic hardware approximation in a RISC-V core. It implements CSR-controlled, per-execution-unit approximate arithmetic (adder and multiplier) and a hierarchical 32×32 multiplier, evaluating post-synthesis metrics at 45nm and 500MHz. The study reports an average run-time energy efficiency improvement of about 9.21% and specific stage- and operation-level power reductions, demonstrating the practicality of hardware-accelerated approximation for embedded workloads. The findings highlight the potential of programmable approximation to tighten the accuracy-power trade-off in modern embedded processors, with avenues for broader architectural integration and real-time energy management.

Abstract

The limited energy available in most embedded systems poses a significant challenge in enhancing the performance of embedded processors and microcontrollers. One promising approach to address this challenge is the use of approximate computing, which can be implemented in both hardware and software layers to balance the trade-off between performance and power consumption. In this study, the impact of dynamic hardware approximation methods on the run-time energy efficiency of a RISC-V embedded processor with specialized features for approximate computing is investigated. The results indicate that the platform achieves an average energy efficiency of 13.3 pJ/instruction at a 500MHz clock frequency adhering approximation in 45nm CMOS technology. Compared to accurate circuits and computation, the approximate computing techniques in the processing core resulted in a significant improvement of 9.21% in overall energy efficiency, 60.83% in multiplication instructions, 14.64% in execution stage, and 9.23% in overall power consumption.

Paper Structure

This paper contains 8 sections, 11 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Experimental Setup
  4. Dynamic Accuracy-Controllable Carry Select Adder
  5. Dynamic Accuracy-Controllable Array Multiplier
  6. Hierarchical 32×32 Approximate Multiplier Design
  7. Results and Comparison
  8. Conclusion

Figures (11)

  • Figure 1: Execution stage high-level block diagram of the processor including accurate and approximate arithmetic circuits
  • Figure 2: Error control, circuit switching, and hardware approximation level determination based on custom CSR values in EXE stage of processor
  • Figure 3: Error controllable low-power and fast carry select adder
  • Figure 4: Proposed full-adder with error signal used in 4-bit ripple carry adders of the CSA circuit
  • Figure 5: 8-bit multiplier's high level block diagram
  • ...and 6 more figures