Millikelvin Si-MOSFETs for Quantum Electronics

Abstract

Large power consumption of silicon CMOS electronics is a challenge in very-large-scale integrated circuits and a major roadblock to fault-tolerant quantum computation. Matching the power dissipation of Si-MOSFETs to the thermal budget at deep cryogenic temperatures, below 1 K, requires switching performance beyond levels facilitated by currently available CMOS technologies. We have manufactured fully depleted silicon-on-insulator MOSFETs tailored for overcoming the power dissipation barrier towards sub-1 K applications. With these cryo-optimized transistors we achieve a major milestone of reaching subthreshold swing of 0.3 mV/dec at 420 mK, thereby enabling very-large-scale integration of cryo-CMOS electronics for ultra-low temperature applications.

Figures (4)

• Figure 1: Examples of heterogeneous and monolithic integration. a Photograph of a flip-chip assembly of hybrid classical and quantum chiplets, bonded to a I/O board. b False colored SEM micrograph of a planar cryogenic quantum IC, that could be used as a chiplet in a, containing SiMOS qubit devices and digital CMOS logic blocks for signal demultiplexing and control. MOSFET devices from the IC blocks, highlighted in green and red, are characterized in this work with respect to switching metrics
• Figure 2: FD-SOI MOSFET transport at variable temperature, $I_d(V_g)$ transfer characteristics for a p-MOSFET (a, $V_{ds}=100$ mV), and an n-MOSFET (b, $V_{ds}=25$ mV) between 280 K and 420 mK. The arrows in the legend indicate the sweep direction of $V_g$ (see also Fig. 3 for details). Raw data is plotted in the inset panels and transfer characteristics at 420 mK, 77 K, and 280 K is highlighted in the main panel. The curves in the main panel are fitted to Eq. 3 ($J_\mathrm{ds,i}$, arb. unit) to extract $SS$, and $v_i$. c,e: $v_i(V_g)$ above threshold, all values are normalized to the subthreshold value at 280 K. In e the measured mobility for a n-Hall-bar with the same $C_\text{ox}$ is plotted for comparison. d,f: $SS(T)$ and $V_\mathrm{th}(T)$ plotted against temperature. Adjusted thermionic limits $SS_i(T)=s_i\mathrm{ln}(10) k_{B} T/e$ are plotted with dashed lines for comparison.
• Figure 3: Sub-Kelvin FD-SOI MOSFET transport, $I_d(V_g)$ transfer characteristics for a p-MOSFET (a, $V_{ds}=100$ mV), and an n-MOSFET (b, $V_{ds}=20$ mV) at 420 mK and 4.2 K. The arrows in the legend indicate the sweep direction of $V_g$. Inset of a: $I_d(V_g)$ of two p-MOSFETs from different wafer batches with different channel width to gate length ratio w/l. Inset of b: $I_d(V_g)$ of two n-MOSFETs from different wafer batches with the same w/l but different $V_{ds}$ magnitude. c,e$I_d(V_g)$ transfer characteristics are measured at 420 mK at variable $V_\text{ds}$. d,f$SS(V_\text{ds})$ at 420 mK extracted by fitting $I_d(V_g)$ in the subthreshold region.
• Figure 4: Dynamic power consumption per unit frequency in MHz and limit frequency $f_{max}$ of an inverter with fan-out of 4 inverters. Both n-MOSFETs and p-MOSFETs have a gate length of 50 nm and the power displayed on the left axis is the normalized power per different unit widths 50 nm (n-MOSFET) and 150 nm (p-MOSFET) to match their on-state resistance.