CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence

TL;DR

CktGen reframes analog circuit design as specification-conditioned generation, learning a joint latent space for discretized specifications and circuit topologies. It combines a transformer-based circuit VAE, a specification encoder, contrastive and classifier-guided alignment, and a GPT-like circuit generator to produce diverse, specification-consistent circuits. Test-time Bayesian multi-armed bandit optimization searches the learned latent space for high-FoM designs that meet target specs, without retraining. Empirical results on Ckt-Bench datasets show state-of-the-art performance in conditional generation, reconstruction, and unconditional generation, with strong clustering, high spec-consistency, and competitive efficiency. The work also outlines avenues for closed-loop evaluation, cross-domain generalization, and LLM-assisted integration within industrial EDA workflows.

Abstract

The automatic synthesis of analog circuits presents significant challenges. Most existing approaches formulate the problem as a single-objective optimization task, overlooking that design specifications for a given circuit type vary widely across applications. To address this, we introduce specification-conditioned analog circuit generation, a task that directly generates analog circuits based on target specifications. The motivation is to leverage existing well-designed circuits to improve automation in analog circuit design. Specifically, we propose CktGen, a simple yet effective variational autoencoder that maps discretized specifications and circuits into a joint latent space and reconstructs the circuit from that latent vector. Notably, as a single specification may correspond to multiple valid circuits, naively fusing specification information into the generative model does not capture these one-to-many relationships. To address this, we decouple the encoding of circuits and specifications and align their mapped latent space. Then, we employ contrastive training with a filter mask to maximize differences between encoded circuits and specifications. Furthermore, classifier guidance along with latent feature alignment promotes the clustering of circuits sharing the same specification, avoiding model collapse into trivial one-to-one mappings. By canonicalizing the latent space with respect to specifications, we can search for an optimal circuit that meets valid target specifications. We conduct comprehensive experiments on the open circuit benchmark and introduce metrics to evaluate cross-model consistency. Experimental results demonstrate that CktGen achieves substantial improvements over state-of-the-art methods.

Figures (14)

• Figure 1: Overview of the CktGen framework for specification-conditioned analog circuit generation and optimization. (a) Joint representation learning. Performance specifications (gain $s_{\text{Gain}}$, bandwidth $s_{\text{BW}}$, and phase margin $s_{\text{PM}}$) are discretized into interval-based classes, grouping circuits by their joint specification class $\bm{s}$. Dedicated encoders map circuits and specifications into a canonical joint latent space. Contrastive training and classifier guidance enforce discriminative boundaries between classes while preserving those within-class cohesion, enabling one-to-many mapping from specifications to diverse circuits. The circuit generator $\mathcal{G}$ synthesizes circuits from specification latent vectors. (b) Test-time optimization. The specific design requirements are modeled as inequality constraints defined by target specification thresholds $\bm{s}^*$ for gain, bandwidth, and PM (i.e., $s_{\text{Gain}} > s^*_{\text{Gain}}$, $s_{\text{BW}} > s^*_{\text{BW}}$, and $s_{\text{PM}} > s^*_{\text{PM}}$), defining a feasible region in the learned latent space. The framework identifies valid joint specification classes that overlap with or approximate this feasible region, reporting an out-of-domain error if none exist. For valid cases, a Bayesian multi-armed bandit (MAB) algorithm performs test-time optimization without model retraining, iteratively searching the latent space, sampling candidates, generating circuits via $\mathcal{G}$, and evaluating their figure of merit (FoM) via a surrogate model. The algorithm adaptively refines its search strategy based on observed FoM values, converging to an optimal circuit that meets the target specification. $\mathcal{E}^{\text{ckt}}$: a transformer-based variational autoencoder for circuits; $\mathcal{E}^{\text{spec}}$: a multilayer perceptron encoder for specifications; $\bm{s}^1, \ldots, \bm{s}^n$: all the joint specification classes in the training dataset, $n$: the is number of the joint specification classes in the dataset range; $\bm{z}_1,\ldots,\bm{z}_n$: latent vectors sampled for each joint specification class; $s^{*}_{\text{Gain}}$, $s^{*}_{\text{BW}}$, and $s^{*}_{\text{PM}}$: target specification thresholds for gain, bandwidth and phase margin, respectively; $\bm{s}^k$: the $k$-th valid specification candidate in the dataset range that meets the threshold ($k=1, 2, \ldots, k_{\text{total}}$, with $k_{\text{total}}$ being the total number of available candidates); $s^{k}_{\text{Gain}}$, $s^{k}_{\text{BW}}$, and $s^{k}_{\text{PM}}$: the gain, bandwidth, and phase margin of the $k$th valid specification class candidate, respectively.
• Figure 2: Overview of the CktGen architecture. The model consists of four modules: (a) a circuit encoder $\mathcal{E}^{\text{ckt}}$, (b) a specification encoder $\mathcal{E}^{\text{spec}}$, (c) latent space alignment, and (d) a circuit generator $\mathcal{G}$. The circuit encoder and specification encoder map circuits and specifications into a latent space. To cluster circuits with the same specification and distinguish different ones, we employ contrastive training and classifier guidance to train a joint latent space. In the circuit generator, a generative pre-trained transformer (GPT)-like model generates the features of the circuit autoregressively. The definitions of the variables in the figure can be found in Sections \ref{['sec:encoder']} and Sections \ref{['sec:align']}.
• Figure 3: Feature generation scheme in the circuit generator. The projected latent vector $\bm{z}'$ is concatenated with embedded node features before being processed by the transformer decoder. The definitions of the variables in the figure can be found in Section \ref{['sec:generator']}.
• Figure 4: Edge reconstruction mechanism in the circuit generator. Concatenated node embedding is processed to predict directed edge probabilities in an autoregressive manner. The definitions of the variables in the figure can be found in Section \ref{['sec:generator']}.
• Figure 5: Architectural comparison of related models: (a) PACE, (b) CktGNN, (c) conditional VAE generative adversarial network (CVAEGAN), (d) latent diffusion transformer (LDT), (e) surrogate, and (f) our CktGen. $G$: the input circuit DAG; $G'$: the generated circuit DAG; $\mathcal{D}$: discriminator; $\mathcal{L}_{\text{disc}}$: discriminator loss; $\mathcal{L}_{\text{MSE}}$: mean squared error loss; $\bm{z}^{*}$: latent vector with added noise.