Design and In-training Optimization of Binary Search ADC for Flexible Classifiers

TL;DR

This work tackles the high area and power cost of ADCs in flexible electronics for on-sensor classifiers. It introduces a novel Binary Search ADC with a comparator/control-unit design that eliminates the encoder, achieving up to $2\times$ (and up to $5.4\times$ vs Flash) area reduction, plus an in-training pruning strategy that further reduces transistor count by about $5\times$ with less than $1\%$ accuracy loss. The authors extend the approach with a NSGA-II based multi-objective optimization to tailor bespoke, pruned ADCs to the input distributions of MLP/SVM classifiers, validated by high-level area models and circuit simulations on PragmatIC FlexICs. Results show substantial area and power savings while maintaining or improving classification accuracy, enabling efficient, flexible, and low-cost FE sensor systems. These contributions advance the practical deployment of FE for smart sensing and wearables by addressing the ADC bottleneck with hardware-aware, classifier-coupled design.

Abstract

Flexible Electronics (FE) offer distinct advantages, including mechanical flexibility and low process temperatures, enabling extremely low-cost production. To address the demands of applications such as smart sensors and wearables, flexible devices must be small and operate at low supply voltages. Additionally, target applications often require classifiers to operate directly on analog sensory input, necessitating the use of Analog to Digital Converters (ADCs) to process the sensory data. However, ADCs present serious challenges, particularly in terms of high area and power consumption, especially when considering stringent area and energy budget. In this work, we target common classifiers in this domain such as MLPs and SVMs and present a holistic approach to mitigate the elevated overhead of analog to digital interfacing in FE. First, we propose a novel design for Binary Search ADC that reduces area overhead 2X compared with the state-of-the-art Binary design and up to 5.4X compared with Flash ADC. Next, we present an in-training ADC optimization in which we keep the bare-minimum representations required and simplifying ADCs by removing unnecessary components. Our in-training optimization further reduces on average the area in terms of transistor count of the required ADCs by 5X for less than 1% accuracy loss.

Figures (4)

• Figure 1: Transistor Count Evaluation of the printed classification system.
• Figure 2: Schematic of: a) conventional 3-bit Binary ADC and b) an example of an equivalent bespoke partial/pruned ADC
• Figure 3: Proposed Design. a) Block diagram of a Binary Search ADC. b) Schematic of the proposed design. c) Schematic of the comparator. d) $V_{in}$, $V_{ref}$ in the first stage of comparison, $V_{ref}$ in the second stage of comparison, $V_{ref}$ in the third stage of comparison
• Figure 4: Pareto space of Accuracy vs normalized Area of 2, 3 and 4-bit ADCs.