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A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications

Arvin Delavari, Faraz Ghoreishy, Hadi Shahriar Shahhoseini, Sattar Mirzakuchaki

TL;DR

A novel reconfigurable embed-ded platform named “phoeniX”, using the standard RISC-V ISA, maximizing energy efficiency while maintaining acceptable application-level accuracy is presented, maximizing energy efficiency while maintaining acceptable application-level accuracy.

Abstract

The demand for energy-efficient and high performance embedded systems drives the evolution of new hardware architectures, including concepts like approximate computing. This paper presents a novel reconfigurable embedded platform named "phoeniX", using the standard RISC-V ISA, maximizing energy efficiency while maintaining acceptable application-level accuracy. The platform enables the integration of approximate circuits at the core level with diverse structures, accuracies, and timings without requiring modifications to the core, particularly in the control logic. The platform introduces novel control features, allowing configurable trade-offs between accuracy and energy consumption based on specific application requirements. To evaluate the effectiveness of the platform, experiments were conducted on a set of applications, such as image processing and Dhrystone benchmark. The core with its original execution engine, occupies 0.024mm2 of area, with average power consumption of 4.23mW at 1.1V operating voltage, average energy-efficiency of 7.85pJ per operation at 620MHz frequency in 45nm CMOS technology. The configurable platform with a highly optimized 3-stage pipelined RV32I(E)M architecture, possesses a DMIPS/MHz of 1.89, and a CPI of 1.13, showcasing remarkable capabilities for an embedded processor.

A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications

TL;DR

A novel reconfigurable embed-ded platform named “phoeniX”, using the standard RISC-V ISA, maximizing energy efficiency while maintaining acceptable application-level accuracy is presented, maximizing energy efficiency while maintaining acceptable application-level accuracy.

Abstract

The demand for energy-efficient and high performance embedded systems drives the evolution of new hardware architectures, including concepts like approximate computing. This paper presents a novel reconfigurable embedded platform named "phoeniX", using the standard RISC-V ISA, maximizing energy efficiency while maintaining acceptable application-level accuracy. The platform enables the integration of approximate circuits at the core level with diverse structures, accuracies, and timings without requiring modifications to the core, particularly in the control logic. The platform introduces novel control features, allowing configurable trade-offs between accuracy and energy consumption based on specific application requirements. To evaluate the effectiveness of the platform, experiments were conducted on a set of applications, such as image processing and Dhrystone benchmark. The core with its original execution engine, occupies 0.024mm2 of area, with average power consumption of 4.23mW at 1.1V operating voltage, average energy-efficiency of 7.85pJ per operation at 620MHz frequency in 45nm CMOS technology. The configurable platform with a highly optimized 3-stage pipelined RV32I(E)M architecture, possesses a DMIPS/MHz of 1.89, and a CPI of 1.13, showcasing remarkable capabilities for an embedded processor.
Paper Structure (10 sections, 2 equations, 7 figures, 10 tables)

This paper contains 10 sections, 2 equations, 7 figures, 10 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Architecture
  4. Execution Engine
  5. Adder/Subtractor
  6. Multiplier
  7. Divider
  8. Experimental Results in Image Processing Application
  9. Implementation and Comparison
  10. Conclusion

Figures (7)

  • Figure 1: The phoeniX RISC-V processor block diagram
  • Figure 2: Proposed processor's execution units structure
  • Figure 3: Circuit result selection logic in core’s execution units according to the respective CSR of each module
  • Figure 4: Proposed Platform’s Execution Engine Control Status Registers General Format
  • Figure 5: Sample “Factorial” RISC-V assembly code utilizing mulcsr to select the approximate circuit and setting error level
  • ...and 2 more figures