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SAMIPS: A Synthesised Asynchronous Processor

Qianyi Zhang, Georgios Theodoropoulos

TL;DR

This paper presents SAMIPS, an entirely asynchronous MIPS microprocessor synthesized in the CSP-based Balsa HDL, tackling clock distribution, power, and hazard challenges inherent to synchronous designs. The authors detail how MIPS R3000’s five-stage datapath and ISA are translated into an asynchronous, handshake-driven pipeline, including a novel data-hazard forwarding mechanism and a distributed, multi-colour control algorithm for branches and interrupts. They provide a comprehensive evaluation across behavioural, gate, and physical levels, comparing SAMIPS to both synchronous MIPS and other asynchronous implementations, and show that automated synthesis via Balsa yields meaningful performance gains with careful modelling. The work demonstrates that high-level CSP-based design flow can produce practical asynchronous processors, offering a roadmap for future asynchronous cores and insights into optimising hazard handling and arbitration in self-timed systems.

Abstract

Miniaturisation and ever increasing clock speeds pose significant challenges to synchronous VLSI design with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Asynchronous logic promises to alleviate these challenges however its development and adoption has been hindered by the lack of mature design tools. Balsa is a response to this gap, encompassing a CSP-based asynchronous hardware description language and a framework for automatically synnthesising asynchronous circuits. This paper discusses SAMIPS, an asynchronous implementation of the MIPS microprocessor and the first full scale asynchronous microprocessor to be synthesised in Balsa. The objectives of the paper are twofold: first to provide a holistic description of SAMIPS and its components, the approach that it has been followed for the asynchronisation of MIPS and the innovative solutions that have been developed to address hazard challenges and a quantitative performance analysis of the system; secondly, to provide insights about the effectiveness of Balsa as a hardware description language and synthesis system.

SAMIPS: A Synthesised Asynchronous Processor

TL;DR

This paper presents SAMIPS, an entirely asynchronous MIPS microprocessor synthesized in the CSP-based Balsa HDL, tackling clock distribution, power, and hazard challenges inherent to synchronous designs. The authors detail how MIPS R3000’s five-stage datapath and ISA are translated into an asynchronous, handshake-driven pipeline, including a novel data-hazard forwarding mechanism and a distributed, multi-colour control algorithm for branches and interrupts. They provide a comprehensive evaluation across behavioural, gate, and physical levels, comparing SAMIPS to both synchronous MIPS and other asynchronous implementations, and show that automated synthesis via Balsa yields meaningful performance gains with careful modelling. The work demonstrates that high-level CSP-based design flow can produce practical asynchronous processors, offering a roadmap for future asynchronous cores and insights into optimising hazard handling and arbitration in self-timed systems.

Abstract

Miniaturisation and ever increasing clock speeds pose significant challenges to synchronous VLSI design with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Asynchronous logic promises to alleviate these challenges however its development and adoption has been hindered by the lack of mature design tools. Balsa is a response to this gap, encompassing a CSP-based asynchronous hardware description language and a framework for automatically synnthesising asynchronous circuits. This paper discusses SAMIPS, an asynchronous implementation of the MIPS microprocessor and the first full scale asynchronous microprocessor to be synthesised in Balsa. The objectives of the paper are twofold: first to provide a holistic description of SAMIPS and its components, the approach that it has been followed for the asynchronisation of MIPS and the innovative solutions that have been developed to address hazard challenges and a quantitative performance analysis of the system; secondly, to provide insights about the effectiveness of Balsa as a hardware description language and synthesis system.
Paper Structure (69 sections, 7 equations, 57 figures, 22 tables)

This paper contains 69 sections, 7 equations, 57 figures, 22 tables.

Table of Contents

  1. Introduction
  2. Balsa
  3. Asynchronising MIPS
  4. MIPS R3000 Functional Blocks
  5. Instruction Set
  6. The Datapath
  7. The Control
  8. Exceptions
  9. Data Hazards
  10. Result Forwarding in Synchronous R3000
  11. Asynchronous Result Forwarding in SAMIPS
  12. Data Hazard Detection Table and Queue
  13. The Forwarding Algorithm
  14. FWunit
  15. Example
  16. ...and 54 more sections

Figures (57)

  • Figure 1: Two-place buffer
  • Figure 2: Balsa System
  • Figure 3: Handshake Circuits for buffer of Figure \ref{['Two-place buffer']}
  • Figure 4: Balsa Backend
  • Figure 5: R3000 Function Block
  • ...and 52 more figures