A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators

TL;DR

Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.

Abstract

In this work, we present a novel non-volatile spin transfer torque (STT) assisted spin-orbit torque (SOT) based ternary content addressable memory (TCAM) with 5 transistors and 2 magnetic tunnel junctions (MTJs). We perform a comprehensive study of the proposed design from the device-level to application-level. At the device-level, various write characteristics such as write error rate, time, and current have been obtained using micromagnetic simulations. The array-level search and write performance have been evaluated based on SPICE circuit simulations with layout extracted parasitics for bitcells while also accounting for the impact of interconnect parasitics at the 7nm technology node. A search error rate of 3.9x10^-11 is projected for exact search while accounting for various sources of variation in the design. In addition, the resolution of the search operation is quantified under various scenarios to understand the achievable quality of the approximate search operations. Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.

Figures (7)

• Figure 1: 5T-2MTJ SOT-TCAM cell schematic. T1 and T2 are SOT write transistors. T3 and T4 are STT/search transistors. T5 is the discharge transistor for the ML. WWL: write wordline, SWL: search wordline, ML: matchline, WBL: write bitline, SBL: search bitline.
• Figure 2: SOT-TCAM array with search drivers, precharge transistors, and sensing inverter amplifiers.
• Figure 3: Layout for the SOT-TCAM cell with 2 bit-cells sharing the BL contacts. Effective area of a single bit-cell is 0.108um x 0.702um.
• Figure 4: (a) Write error rate plotted against the write delay for STT-assisted SOT switching. SOT current is applied for the initial 1 ns. (b) Distribution of mz at the end of 1 ns SOT pulse for varying values of SOT spin current.
• Figure 5: ML delay data distribution for 1000 Monte Carlo simulations, considering Vt and MTJ resistance variation, for single bit mismatch and 32 'X' bit match for a 64x128 SOT-5T CAM array.