Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock

TL;DR

Omni 3D introduces BEOL-compatible 3D logic that interleaves transistors and metal to enable true double-sided routing and intra-cell IM routing. Through DTCO and a dedicated physical-design flow, the work demonstrates that Omni 3D can achieve about $2.0\times$ energy-delay product reduction and up to $1.5\times$ area reduction vs CFETs with BSPDNs, across CNFET and Si FET technologies, with the DO pin-access variant providing the strongest overall gains. The approach relies on a BEOL-aware channel, a split PDN with power rails on opposite sides, and a three-tier routing strategy, supported by modified PDK definitions and a clustering-based netlist balancing algorithm. The results indicate significant potential for BEOL-compatible 3D logic in energy-efficient computing, while also identifying practical challenges in EDA tooling and multi-tier design that warrant further exploration.

Abstract

This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves metal layers for both signal/power with FETs in 3D (i.e., nFETs and pFETs are stacked in 3D). Thus, signal/power routing layers have fine-grained, all-sided access to the FET active regions maximizing 3D standard cell design flexibility. This is in sharp contrast to approaches such as back-side power delivery networks (BSPDNs), complementary FETs (CFETs), and stacked FETs. Importantly, the routing flexibility of Omni 3D is enabled by double-side routing and an interleaved metal (IM) layer for inter- and intra-cell routing, respectively. In this work, we explore Omni 3D variants (e.g., both with and without the IM layer) and optimize these variants using a virtual-source BEOL-FET compact model. We establish a physical design flow that efficiently utilizes the double-side routing in Omni 3D and perform a thorough design-technology-co-optimization (DTCO) of Omni 3D device architecture on several design points. From our design flow, we project 2.0x improvement in the energy-delay product and 1.5x reduction in area compared to the state-of-the-art CFETs with BSPDNs.

Figures (15)

• Figure 1: Omni 3D features in contrast to CFET: 3D illustration of (a) a CFET inverter (INV) with BPR and (b) an Omni 3D INV with near-FET Vdd/Vss to avoid a tall via crossing the lower FET for upper FET power supply. A BEOL-compatible channel naturally enables the bottom pin in Omni 3D. Correspondingly, a top view of (c) 4-track CFET and (d) 3-track Omni 3D INVs with comparable channel width. CFET channel width ($27~nm$) is limited by the channel-to-tall via space and Omni 3D channel width ($28~nm$) is defined by the gate extension; the same gate cut determines the location of a tall via and the gate edge of CFET and Omni 3D, respectively. Omni 3D NOR2 (e) without and (f) with IM present shortened intra-cell connection facilitating IM.
• Figure 2: (a) Benchmark circuits for DTCO: wire-loaded 15-stage FO3 INV RO. Energy vs. delay pareto curves of CFET and Omni 3D from our DTCO framework with (b) CNFETs and (c) Si FETs (results from omni). By coincidence, both channel materials achieve similar EDP benefits in Omni 3D ($\sim1.3\times$). However, the breakdown of $R_{eff}$ and $C_{eff}$ benefits of Omni 3D with (d) carbon nanotube (CNT) and (e) Si are different.
• Figure 3: Front view of (a) Omni 3D and (b) Omni 3D noIM INVs. (c) Their input capacitance breakdown. Capacitance of IM, gate, and S/D affected by IM elimination are color-coded. TM1: top-side metal 1 and BM1: bottom-side metal 1.
• Figure 4: (a) Area of Omni 3D and Omni 3D noIM normalized to corresponding CFETs for 20 basic cells. Area benefits exemplified with MUX top views: (b) CFET - $4$ tracks (T) $\times$$8$ gate pitches (GP), (c) Omni 3D - $3$ T $\times$$7$ GP, and (d) Omni 3D noIM - $3$ T $\times$$8$ GP. MUX 3D illustrations of (e) Omni 3D and (f) Omni 3D noIM.
• Figure 5: (a) Side view of Omni 3D (SIO) routing example and (b) its routing sequential dependency.