Learning Task-Based Trainable Neuromorphic ADCs via Power-Aware Distillation

TL;DR

A data-driven algorithm is introduced that jointly tunes task-based memristive ADCs alongside both digital and analog processing, and is shown to enhance accuracy by up to 27% and reduce power consumption by up to 66% compared to uniform ADCs.

Abstract

The ability to process signals in digital form depends on analog-to-digital converters (ADCs). Traditionally, ADCs are designed to ensure that the digital representation closely matches the analog signal. However, recent studies have shown that significant power and memory savings can be achieved through task-based acquisition, where the acquisition process is tailored to the downstream processing task. An emerging technology for task-based acquisition involves the use of memristors, which are considered key enablers for neuromorphic computing. Memristors can implement ADCs with tunable mappings, allowing adaptation to specific system tasks or power constraints. In this work, we study task-based acquisition for a generic classification task using memristive ADCs. We consider the unique characteristics of this such neuromorphic ADCs, including their power consumption and noisy read-write behavior, and propose a physically compliant model based on resistive successive approximation register ADCs integrated with memristor components, enabling the adjustment of quantization regions. To optimize performance, we introduce a data-driven algorithm that jointly tunes task-based memristive ADCs alongside both digital and analog processing. Our design addresses the inherent stochasticity of memristors through power-aware distillation, complemented by a specialized learning algorithm that adapts to their unique analog-to-digital mapping. The proposed approach is shown to enhance accuracy by up to 27% and reduce power consumption by up to 66% compared to uniform ADCs. Even under noisy conditions, our method achieves substantial gains, with accuracy improvements of up to 19% and power reductions of up to 57%. These results highlight the effectiveness of our power-aware neuromorphic ADCs in improving system performance across diverse tasks.

Figures (11)

• Figure 1: Neuromorphic sar adc schematic: $(a)$ Overall circuit; $(b)$ Neuron module; $(c)$ Memristive synapse.
• Figure 2: An illustration of a generic task-based acquisition system
• Figure 3: Machine learning model of the neuromorphic task-based acquisition system.
• Figure 4: Illustrations of decision regions and quantization levels of a 3-bit memristive adc: $(a)$ decision regions and their correspondence with memristor weights; $(b)$ a setting that maintains the full range of the ADC; and $(c)$ a setting with collapsing decision regions, reducing the effective quantization levels.
• Figure 5: Approximation of $\text{sign}(x)$ using $\tanh(Ax)$.