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A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping

Brendan Saux, Jonas Borgmans, Johan Raman, Pieter Rombouts

TL;DR

The paper tackles the challenge of achieving high-bandwidth, high-resolution ADC performance with purely VCO-based architectures. It introduces a 1-1 MASH VCO ADC that uses multi-bit estimated error signals from a multi-phase first stage to drive a second VCO stage, enabling second-order noise shaping in an open-loop configuration. A cross-coupled, pseudo-differential second stage and robust error-estimation/refinement strategies mitigate nonlinearity and pulse-width errors, achieving a 3.5 GS/s implementation with SNDR of 67 dB and DR of 68 dB over 109.375 MHz OSR16 bandwidth, and FoM$_{DR}$ of 163 dB in 28 nm CMOS. The work demonstrates the viability of high-bandwidth, purely VCO-based higher-order A/D conversion with competitive power, area, and calibration requirements, enabling fast sensing and communications applications.

Abstract

In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop configuration. A key enabler of the high-bandwidth MASH VCO ADC is the use of a multi-bit estimated error signal. With an OSR of 16, an SNDR of 67 dB and DR of 68 dB are achieved in 109.375 MHz bandwidth. The full-custom pseudo-analog circuits consume 9 mW, while the automatically generated digital circuits consume another 24 mW. A $\mathbf{FoM_{DR} = 163}$ dB and core area of $\mathbf{0.017\,\mathbf{mm}^2}$ are obtained.

A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping

TL;DR

The paper tackles the challenge of achieving high-bandwidth, high-resolution ADC performance with purely VCO-based architectures. It introduces a 1-1 MASH VCO ADC that uses multi-bit estimated error signals from a multi-phase first stage to drive a second VCO stage, enabling second-order noise shaping in an open-loop configuration. A cross-coupled, pseudo-differential second stage and robust error-estimation/refinement strategies mitigate nonlinearity and pulse-width errors, achieving a 3.5 GS/s implementation with SNDR of 67 dB and DR of 68 dB over 109.375 MHz OSR16 bandwidth, and FoM of 163 dB in 28 nm CMOS. The work demonstrates the viability of high-bandwidth, purely VCO-based higher-order A/D conversion with competitive power, area, and calibration requirements, enabling fast sensing and communications applications.

Abstract

In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop configuration. A key enabler of the high-bandwidth MASH VCO ADC is the use of a multi-bit estimated error signal. With an OSR of 16, an SNDR of 67 dB and DR of 68 dB are achieved in 109.375 MHz bandwidth. The full-custom pseudo-analog circuits consume 9 mW, while the automatically generated digital circuits consume another 24 mW. A dB and core area of are obtained.
Paper Structure (20 sections, 10 equations, 29 figures, 3 tables)

This paper contains 20 sections, 10 equations, 29 figures, 3 tables.

Table of Contents

  1. Introduction
  2. MASH VCO A/D Conversion
  3. Multi-Bit Error Estimation
  4. Initial 1-1 MASH VCO Architecture
  5. Analysis and Theoretical Performance
  6. Comparison With Prior Art 1-1 MASH VCO ADCs
  7. Driving the Second Stage
  8. Impact of Nonlinearity in the Second Stage
  9. Architecture With Cross-coupled Estimated Error Signals
  10. Practical Implementation
  11. Influence of Pulse Width Errors
  12. CMOS Circuits
  13. Ring Oscillators
  14. QSD With Error Estimation
  15. Digital Core
  16. ...and 5 more sections

Figures (29)

  • Figure 1: Simplified PFM model of a single-stage VCO ADC showing in-band signals.
  • Figure 2: Conceptual illustration of the performance degradation due to presence of the spurs of the first PFM sideband in the signal bandwidth gutierrez2017pulse.
  • Figure 3: Initial MASH VCO architecture.
  • Figure 4: Illustration of time-domain waveforms of the relevant signals to obtain the estimated error signal $E$.
  • Figure 5: Simplified block diagram of a MASH VCO ADC (black). The equivalent error $N_{NL}$ to model the effect of nonlinearity in the second stage (red) was also added.
  • ...and 24 more figures