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Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness

Zhe Jiang, Shuai Zhao, Ran Wei, Xin Si, Gang Chen, Nan Guan

TL;DR

A robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler, offering a robust and configurable scheduling infrastructure.

Abstract

In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been investigated and developed. However, these solutions are often fragile, due to unforeseen timing defects. In this paper, we propose a robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler. The ETSs limit the impact of timing defects between tasks, and the scheduler prioritises ETSs based on their importance, offering a robust and configurable scheduling infrastructure. Based on the hardware design, we present an ETS-based timing-accurate I/O schedule, with the ETS parameters configured to further enhance robustness against timing defects. Experiments show the proposed I/O control method outperforms the state-of-the-art method in terms of timing accuracy and robustness without introducing significant overhead.

Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness

TL;DR

A robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler, offering a robust and configurable scheduling infrastructure.

Abstract

In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been investigated and developed. However, these solutions are often fragile, due to unforeseen timing defects. In this paper, we propose a robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler. The ETSs limit the impact of timing defects between tasks, and the scheduler prioritises ETSs based on their importance, offering a robust and configurable scheduling infrastructure. Based on the hardware design, we present an ETS-based timing-accurate I/O schedule, with the ETS parameters configured to further enhance robustness against timing defects. Experiments show the proposed I/O control method outperforms the state-of-the-art method in terms of timing accuracy and robustness without introducing significant overhead.
Paper Structure (24 sections, 4 theorems, 2 equations, 10 figures, 4 tables, 1 algorithm)

This paper contains 24 sections, 4 theorems, 2 equations, 10 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. ROTA-I/O: Overview
  3. Top-level Concepts
  4. ISA Support
  5. Programming Model
  6. Integrating ROTA-I/O into a SoC
  7. ROTA-I/O: Micro-architecture
  8. I/O Pool
  9. Scheduling Engine (SE)
  10. Design Trade-Offs
  11. ROTA-Sched: An ETS-based Schedule
  12. System Model
  13. Allocation and Scheduling of Jobs in ETSs
  14. Configuration of ETS Parameters
  15. Evaluation
  16. ...and 9 more sections

Key Result

Lemma 1

For a given $S_k \in S^* \cup S^\neg$, the highest delay that $S_k$ can incur is $\Upsilon_k = \min\{ d_i^j - \theta_i^j - C_i | ~\forall \tau_i^j \in G(S_k)\}$.

Figures (10)

  • Figure 1: A conceptual overview of ROTA-I/O(square: router; circle: core; rectangle: ROTA-I/O; triangle: device; curved arrows: tasks with different timing guarantees; ETS: Execution Timer Server): (a) ROTA-I/O serves as a co-processor, enabling I/O management at hardware; (b) ROTA-I/O features sets of ETSs and a two-level scheduler, limiting the impact of timing defects while offering a configurable scheduling infrastructure; (c) ROTA-Sched schedules tasks and configures ROTA-I/O using (d) the dedicated ISA; (e) an illustrative mechanism of ROTA-Sched, improving I/O robustness and accuracy.
  • Figure 2: Top-level micro-architecture of ROTA-I/O(Mini-D: mini decoder; Prio-S/T: priority of server/task; TID: task ID; TID-SCH: scheduled TID): a tasks are maintained in an SRAM-based I/O pool, allowing prioritisation; b nested schedulers prioritise the I/O tasks hierarchically; c scheduled tasks are translated into physical signals for the device control.
  • Figure 3: G-SE micro-architecture (refer to Fig. \ref{['fig:top-micro']} for legends; SID-SCH: scheduled ETS ID; C: comparator): a SCs are one-to-one associated to an ETS, featuring a parameter register to maintain the ETS's priority, and b a pair of count-down timers to manage the budget; c the ETSs's status is collected and prioritised, and the results are broadcasted to L-SEs.
  • Figure 4: L-SE micro-architecture (refer to Fig. \ref{['fig:top-micro']} for legends; T-Para: task parameters; TID-SCH: scheduled task ID): a task parameters in the same ETS are stored in a TIB, implemented using a register chain; b all entries of the TIB are compared, identifying the task with the highest priority and returning the TID to G-SE, forming the final scheduling decision.
  • Figure 5: Example timing-accurate models of I/O tasks (x-axis: time relative to the release of a task; y-axis: the resulting I/O control quality given a time instant $t$).
  • ...and 5 more figures

Theorems & Definitions (8)

  • Lemma 1
  • proof
  • Lemma 2
  • proof
  • Theorem 1
  • proof
  • Theorem 2
  • proof