An Efficient General-Purpose Optical Accelerator for Neural Networks

TL;DR

A hybrid GOA architecture is proposed to enhance the mapping efficiency of neural networks onto the GOA using independent MZI modules connected with microring resonators, so that they can be combined to process large neural networks efficiently.

Abstract

General-purpose optical accelerators (GOAs) have emerged as a promising platform to accelerate deep neural networks (DNNs) due to their low latency and energy consumption. Such an accelerator is usually composed of a given number of interleaving Mach-Zehnder- Interferometers (MZIs). This interleaving architecture, however, has a low efficiency when accelerating neural networks of various sizes due to the mismatch between weight matrices and the GOA architecture. In this work, a hybrid GOA architecture is proposed to enhance the mapping efficiency of neural networks onto the GOA. In this architecture, independent MZI modules are connected with microring resonators (MRRs), so that they can be combined to process large neural networks efficiently. Each of these modules implements a unitary matrix with inputs adjusted by tunable coefficients. The parameters of the proposed architecture are searched using genetic algorithm. To enhance the accuracy of neural networks, selected weight matrices are expanded to multiple unitary matrices applying singular value decomposition (SVD). The kernels in neural networks are also adjusted to use up the on-chip computational resources. Experimental results show that with a given number of MZIs, the mapping efficiency of neural networks on the proposed architecture can be enhanced by 21.87%, 21.20%, 24.69%, and 25.52% for VGG16 and Resnet18 on datasets Cifar10 and Cifar100, respectively. The energy consumption and computation latency can also be reduced by over 67% and 21%, respectively.

Figures (10)

• Figure 1: (a) MZI structure and the interleaving MZI array for a 4$\times$4 unitary matrix. (b) Mapping a 4$\times$4 unitary matrix onto an 8$\times$8 interleaving MZI array.
• Figure 2: MRR as (a) a switch and (b) an adder using WDM technique.
• Figure 3: The proposed architecture, composing of small $k\times k$ MZI modules connected by MRRs and peripheral devices, where m and n are the row number and column number of the MZI modules.
• Figure 4: (a) Matrix approximation with one unitary matrix. (b) Restoring the original matrix with two unitary matrices.
• Figure 5: Mapping five weight matrices from VGG16 onto a GOA where m=20, n=12, k=63. The GOA has 20 rows and 12 columns of 63$\times$63 MZI modules and the interconnections are omitted for simplicity. On the left side, an 256$\times$1152 matrix is mapped onto 6$\times$19 MZI modules, called a 256$\times$1152 cluster. Mappings of clusters of different weight matrices are shown on the right side. The clusters are rotated by 90 degrees for mapping, to adapt to the input signals from the left side.