MPAI: A Co-Processing Architecture with MPSoC & AI Accelerators for Vision Applications in Space

TL;DR

The paper tackles the challenge of deploying fast, power-efficient AI on-board spacecraft by proposing MPAI, a heterogeneous co-processing architecture that combines an UltraScale+ MPSoC with AI accelerators such as the MyriadX VPU and Edge TPU. It introduces partition-aware, mixed-precision inference where convolutional layers run on a DPU with $INT8$ precision while heavier fully connected layers run on a VPU with $FP16$, enabling efficient handling of networks with varying complexity. Preliminary results across multiple boards and networks show that the DPU can outperform other accelerators in latency, and that the MPAI configuration substantially reduces inference time while keeping accuracy close to baseline. The work demonstrates the practicality of on-board, configurable AI acceleration for space vision tasks and outlines future directions in virtualization, model partitioning guidelines, and broader workload evaluation.

Abstract

The emerging need for fast and power-efficient AI/ML deployment on-board spacecraft has forced the space industry to examine specialized accelerators, which have been successfully used in terrestrial applications. Towards this direction, the current work introduces a very heterogeneous co-processing architecture that is built around UltraScale+ MPSoC and its programmable DPU, as well as commercial AI/ML accelerators such as MyriadX VPU and Edge TPU. The proposed architecture, called MPAI, handles networks of different size/complexity and accommodates speed-accuracy-energy trade-offs by exploiting the diversity of accelerators in precision and computational power. This brief provides technical background and reports preliminary experimental results and outcomes.

Figures (2)

• Figure 1: Co-processing architecture with MPSoC and VPU/TPU AI accelerator.
• Figure 2: Inference throughput of AI accelerators.