RTLRewriter: Methodologies for Large Models aided RTL Code Optimization

TL;DR

This work tackles the challenge of RTL code optimization in early circuit design, where manual rewrites and limited compiler support hinder handling complex patterns. It proposes RTLRewriter, an end-to-end pipeline that partitions large RTL designs, performs multi-modal program analysis, leverages retrieval-augmented guidance, and uses a cost-aware Monte Carlo Tree Search to drive rewriting while a fast verification pipeline filters ineffective results. Key contributions include the first LLM-aided RTL optimization framework, two benchmarking suites representing industry and academic needs, and extensive experiments showing improvements over strong baselines such as Yosys and E-graph, particularly when combined with partitioning and fuzz-based verification. The approach promises faster iteration, reduced verification costs, and broader applicability to real-world designs, bridging academia and industry in RTL optimization.

Abstract

Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization relies heavily on manual efforts by skilled engineers, often requiring multiple iterations based on synthesis feedback. In contrast, existing compiler-based methods fall short in addressing complex designs. This paper introduces RTLRewriter, an innovative framework that leverages large models to optimize RTL code. A circuit partition pipeline is utilized for fast synthesis and efficient rewriting. A multi-modal program analysis is proposed to incorporate vital visual diagram information as optimization cues. A specialized search engine is designed to identify useful optimization guides, algorithms, and code snippets that enhance the model ability to generate optimized RTL. Additionally, we introduce a Cost-aware Monte Carlo Tree Search (C-MCTS) algorithm for efficient rewriting, managing diverse retrieved contents and steering the rewriting results. Furthermore, a fast verification pipeline is proposed to reduce verification cost. To cater to the needs of both industry and academia, we propose two benchmarking suites: the Large Rewriter Benchmark, targeting complex scenarios with extensive circuit partitioning, optimization trade-offs, and verification challenges, and the Small Rewriter Benchmark, designed for a wider range of scenarios and patterns. Our comparative analysis with established compilers such as Yosys and E-graph demonstrates significant improvements, highlighting the benefits of integrating large models into the early stages of circuit design. We provide our benchmarks at https://github.com/yaoxufeng/RTLRewriter-Bench.

Figures (7)

• Figure 1: Rewriting example and Rewriter Pipeline.
• Figure 2: Circuit Partition Pipeline
• Figure 3: RTL Rewriting Pipeline
• Figure 4: Multi-modal Program Analysis
• Figure 5: C-MCTS Pipeline