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LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection

Hao-Chiang Shao, Guan-Yu Chen, Yu-Hsien Lin, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu

TL;DR

LithoHoD tackles IC layout hotspot detection by integrating a physics-informed lithography simulator (LithoNet) with a CNN-based detector (RetinaNet) through Cross-Model Feature Fusion and attention mechanisms. By learning the triune relationship among layout patterns, lithography-induced deformations, and hotspot ground truths, the framework detects potential hotspots based on predicted deformation maps alongside known hotspot patterns. The method introduces a channel-wise attention module, three CMF fusion blocks, and a cross-attention mechanism to align deformation features with multi-scale layout features, achieving superior recall and AUC on ICCAD16 and the real-world UMC20K dataset. This simulator-guided approach improves generalization to unseen designs and demonstrates the value of combining physics-based simulation with deep learning for IC design-for-manufacturability tasks, albeit with a modest increase in compute time.$ $

Abstract

Recent advances in VLSI fabrication technology have led to die shrinkage and increased layout density, creating an urgent demand for advanced hotspot detection techniques. However, by taking an object detection network as the backbone, recent learning-based hotspot detectors learn to recognize only the problematic layout patterns in the training data. This fact makes these hotspot detectors difficult to generalize to real-world scenarios. We propose a novel lithography simulator-powered hotspot detection framework to overcome this difficulty. Our framework integrates a lithography simulator with an object detection backbone, merging the extracted latent features from both the simulator and the object detector via well-designed cross-attention blocks. Consequently, the proposed framework can be used to detect potential hotspot regions based on I) the variation of possible circuit shape deformation estimated by the lithography simulator, and ii) the problematic layout patterns already known. To this end, we utilize RetinaNet with a feature pyramid network as the object detection backbone and leverage LithoNet as the lithography simulator. Extensive experiments demonstrate that our proposed simulator-guided hotspot detection framework outperforms previous state-of-the-art methods on real-world data.

LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection

TL;DR

LithoHoD tackles IC layout hotspot detection by integrating a physics-informed lithography simulator (LithoNet) with a CNN-based detector (RetinaNet) through Cross-Model Feature Fusion and attention mechanisms. By learning the triune relationship among layout patterns, lithography-induced deformations, and hotspot ground truths, the framework detects potential hotspots based on predicted deformation maps alongside known hotspot patterns. The method introduces a channel-wise attention module, three CMF fusion blocks, and a cross-attention mechanism to align deformation features with multi-scale layout features, achieving superior recall and AUC on ICCAD16 and the real-world UMC20K dataset. This simulator-guided approach improves generalization to unseen designs and demonstrates the value of combining physics-based simulation with deep learning for IC design-for-manufacturability tasks, albeit with a modest increase in compute time.

Abstract

Recent advances in VLSI fabrication technology have led to die shrinkage and increased layout density, creating an urgent demand for advanced hotspot detection techniques. However, by taking an object detection network as the backbone, recent learning-based hotspot detectors learn to recognize only the problematic layout patterns in the training data. This fact makes these hotspot detectors difficult to generalize to real-world scenarios. We propose a novel lithography simulator-powered hotspot detection framework to overcome this difficulty. Our framework integrates a lithography simulator with an object detection backbone, merging the extracted latent features from both the simulator and the object detector via well-designed cross-attention blocks. Consequently, the proposed framework can be used to detect potential hotspot regions based on I) the variation of possible circuit shape deformation estimated by the lithography simulator, and ii) the problematic layout patterns already known. To this end, we utilize RetinaNet with a feature pyramid network as the object detection backbone and leverage LithoNet as the lithography simulator. Extensive experiments demonstrate that our proposed simulator-guided hotspot detection framework outperforms previous state-of-the-art methods on real-world data.
Paper Structure (20 sections, 13 equations, 10 figures, 8 tables)

This paper contains 20 sections, 13 equations, 10 figures, 8 tables.

Figures (10)

  • Figure 1: Differences in the design concepts between traditional hotspot detectors and ours. While a traditional hotspot detector is trained as a naive hotspot pattern recognizer with the supervision of hotspot ground-truths, our design aims to learn the triune relationship among layout, fabrication outcomes, and hotspots. This design enables LithoHoD to recognize local design patterns that may lead to highly similar circuit appearances of hotspots. As a result, LithoHoD functions as a versatile hotspot detector capable of identifying not only layout defect patterns but also considering circuit shape deformations due to a fabrication process to pinpoint potential hotspots. Hotspot regions in this figure are indicated with red boxes.
  • Figure 2: Framework of the proposed LithoHoD. This framework comprises two primary functional components: a pretrained lithography simulator (LithoNet) and a trainable object detector (Channel-attention-enhanced RetinaNet). This design includes a channel-wise attention (C-Attn) module and three cross-model feature fusion (CMF) modules. The C-Attn module enhances the representability of the feature tensor used in the RetinaNet backbone. In contrast, the CMF modules facilitate the integration of the shape-deformation feature $f_\mathrm{de}$ with detection features $f_{\mathrm{py},l}$ in three distinct observation scales extracted by the feature pyramid network (FPN). Here, the tensor $\mathrm{C}_l$ corresponds to the output of the $l$-th convolution stage, and its dimension is $2^l$ times lower than the original input. $\mathrm{P}_l$ is the tensor derived by the pyramid structure with the same spatial dimension as $C_l$. Note that, i) the FPN in RetinaNet omits the $P_2$ and $P_1$ layers in its design, ii) our implementation removes the $P_6$ and $P_7$ layers of the original FPN used in RetinaNet, and iii) the architecture of the detector module ClsBbx, consisting of a classification subnet and a box regression subnet, is detailed in Table \ref{['table:detectormodule']}.
  • Figure 3: Proposed Cross-Model Feature Fusion (CMF) module. This module is designed to generate a fused model-guided feature for layout hotspot detection. To this end, CMF comprises two self-attention modules and one cross-attention module. Specifically, one self-attention module enhances the shape-deformation feature (i.e., the deformation map $f_{\mathrm{de}}$) generated by the pre-trained lithography simulator. Besides, the other self-attention module processes the pattern feature (i.e., the pyramid feature $f_{\mathrm{py},l}$ for object detection) derived from the feature pyramid network of the channel-attention-enhanced RetinaNet backbone. The two enhanced and adapted feature tensors are then fed into the cross-attention module for cross-model feature fusion. Note that the two self-attention modules share the same architecture, and the dimension of each feature tensor used in the CMF module is shown in Table \ref{['tab:tensordimension']}.
  • Figure 4: Examples from ICCAD16 dataset. Left: Case-2. Middle: Case-3. Right: Case-4. Each case consists of a layout sample, with its left-half used for training data and the right-half for testing data. The dimensions of the half-size for Case-2, Case-3, and Case-4 are respectively $6.95 \mu m \times 3.75 \mu m$, $12.91 \mu m \times 10.07 \mu m$, and $79.95 \mu m \times 42.13 \mu m$.
  • Figure 5: Example clips of UMC20K dataset, presented through their lithographic simulation results. The UMC20K dataset comprises 23,007 design clips representing digital and analog circuits, categorized into six subsets.
  • ...and 5 more figures