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Parallel Tempering-Inspired Distributed Binary Optimization with In-Memory Computing

Xiangyi Zhang, Fabian Böhm, Elisabetta Valiante, Moslem Noori, Thomas Van Vaerenbergh, Chan-Woo Yang, Giacomo Pedretti, Masoud Mohseni, Raymond Beausoleil, Ignacio Rozada

TL;DR

Binary optimization on in-memory computing (IMC) hardware benefits from cross-replica cooperation inspired by parallel tempering. The PTIC framework maps replica temperature to a probabilistic local update parameter, enabling low-overhead exchanges of promising solutions across replicas. When applied to SAT with WalkSAT, PTIC-WalkSAT achieves substantial reductions in iterations-to-solution (ITS_{99}) compared with both WalkSAT and PA-WalkSAT, while keeping energy overhead under 1% of total energy. This work suggests PTIC as a general, energy-efficient framework for accelerating IMC solvers across diverse binary-optimization problems.

Abstract

In-memory computing (IMC) has been shown to be a promising approach for solving binary optimization problems while significantly reducing energy and latency. Building on the advantages of parallel computation, we propose an IMC-compatible parallelism framework based on the physics-inspired parallel tempering (PT) algorithm, enabling cross-replica communication to improve the performance of IMC solvers. This framework enables an IMC solver not only to improve performance beyond what can be achieved through parallelization, but also affords greater flexibility for the search process with low hardware overhead. We justify that the framework can be applied to almost any IMC solver. We demonstrate the effectiveness of the framework for the Boolean satisfiability (SAT) problem, using the WalkSAT heuristic as a proxy for existing IMC solvers. The resulting PT-inspired cooperative WalkSAT (PTIC-WalkSAT) algorithm outperforms the standard WalkSAT heuristic in terms of the iterations-to-solution in 84.0% of the tested problem instances and its naïve parallel variant (PA-WalkSAT) does so in 64.9% of the instances, and with a higher success rate in the majority of instances. An estimate of the energy overhead of the PTIC framework for two hardware accelerator architectures indicates that in both cases the overhead of running the PTIC framework would be less than 1% of the total energy required to run each accelerator.

Parallel Tempering-Inspired Distributed Binary Optimization with In-Memory Computing

TL;DR

Binary optimization on in-memory computing (IMC) hardware benefits from cross-replica cooperation inspired by parallel tempering. The PTIC framework maps replica temperature to a probabilistic local update parameter, enabling low-overhead exchanges of promising solutions across replicas. When applied to SAT with WalkSAT, PTIC-WalkSAT achieves substantial reductions in iterations-to-solution (ITS_{99}) compared with both WalkSAT and PA-WalkSAT, while keeping energy overhead under 1% of total energy. This work suggests PTIC as a general, energy-efficient framework for accelerating IMC solvers across diverse binary-optimization problems.

Abstract

In-memory computing (IMC) has been shown to be a promising approach for solving binary optimization problems while significantly reducing energy and latency. Building on the advantages of parallel computation, we propose an IMC-compatible parallelism framework based on the physics-inspired parallel tempering (PT) algorithm, enabling cross-replica communication to improve the performance of IMC solvers. This framework enables an IMC solver not only to improve performance beyond what can be achieved through parallelization, but also affords greater flexibility for the search process with low hardware overhead. We justify that the framework can be applied to almost any IMC solver. We demonstrate the effectiveness of the framework for the Boolean satisfiability (SAT) problem, using the WalkSAT heuristic as a proxy for existing IMC solvers. The resulting PT-inspired cooperative WalkSAT (PTIC-WalkSAT) algorithm outperforms the standard WalkSAT heuristic in terms of the iterations-to-solution in 84.0% of the tested problem instances and its naïve parallel variant (PA-WalkSAT) does so in 64.9% of the instances, and with a higher success rate in the majority of instances. An estimate of the energy overhead of the PTIC framework for two hardware accelerator architectures indicates that in both cases the overhead of running the PTIC framework would be less than 1% of the total energy required to run each accelerator.
Paper Structure (25 sections, 6 equations, 9 figures, 8 tables, 3 algorithms)

This paper contains 25 sections, 6 equations, 9 figures, 8 tables, 3 algorithms.

Table of Contents

  1. Introduction
  2. Background and Preliminaries
  3. Methods
  4. The PTIC Framework
  5. Applying the PTIC Framework to the SAT Problem
  6. The Boolean Satisfiability Problem
  7. The WalkSAT Heuristic
  8. The PTIC-WalkSAT Algorithm
  9. Hardware Implementation for the PTIC Framework
  10. Benchmarking Methodology
  11. The Problem Instances
  12. The Metrics
  13. The Hyperparameters
  14. The WalkSAT Heuristic Baseline
  15. The PA-WalkSAT Algorithm Baseline
  16. ...and 10 more sections

Figures (9)

  • Figure 1: Replica-exchange visualization
  • Figure 2: Exemplary hardware architectures for realizing the PTIC framework within (a) a PUBO and (b) a CAMSAT hardware accelerator for solving SAT problems. Peripherals added to support the PTIC framework are highlighted in yellow.
  • Figure 3: Box plots of the $ITS_{99}$ values for the three algorithms
  • Figure 4: Groupwise cumulative $ITS_{99}$ plots
  • Figure 5: Percentage of instances that fall into each improvement range
  • ...and 4 more figures