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External Memories of PDP Switches for In-Network Implementable Functions Placement: Deep Learning Based Reconfiguration of SFCs

Somayeh Kianpisheh, Tarik Taleb

TL;DR

This work studies in-network VNF placement and SFC reconfiguration using external memories in PDP switches to satisfy ultra-low latency requirements. It formulates a time-slotted optimization that balances IT resource, bandwidth, and reconfiguration costs, and introduces a DRL-based SFC reconfiguration method with static and dynamic filters to cope with dynamic traffic. The proposed SR-EM framework demonstrates improved acceptance ratios and reduced total cost compared with baselines, validating the practicality of RDMA-enabled memory extension for in-network functions. By enabling large VNFs to be hosted closer to the data plane, SR-EM reduces traffic detours and backhaul load, with future directions including energy efficiency enhancements.

Abstract

Network function virtualization leverages programmable data plane switches to deploy in-network implementable functions, to improve QoS. The memories of switches can be extended through remote direct memory access to access external memories. This paper exploits the switches external memories to place VNFs at time intervals with ultra-low latency and high bandwidth demands. The reconfiguration decision is modeled as an optimization to minimize the deployment and reconfiguration cost, while meeting the SFCs deadlines. A DRL based method is proposed to reconfigure service chains adoptable with dynamic network and traffic characteristics. To deal with slow convergence due to the complexity of deployment scenarios, static and dynamic filters are used in policy networks construction to diminish unfeasible placement exploration. Results illustrate improvement in convergence, acceptance ratio and cost.

External Memories of PDP Switches for In-Network Implementable Functions Placement: Deep Learning Based Reconfiguration of SFCs

TL;DR

This work studies in-network VNF placement and SFC reconfiguration using external memories in PDP switches to satisfy ultra-low latency requirements. It formulates a time-slotted optimization that balances IT resource, bandwidth, and reconfiguration costs, and introduces a DRL-based SFC reconfiguration method with static and dynamic filters to cope with dynamic traffic. The proposed SR-EM framework demonstrates improved acceptance ratios and reduced total cost compared with baselines, validating the practicality of RDMA-enabled memory extension for in-network functions. By enabling large VNFs to be hosted closer to the data plane, SR-EM reduces traffic detours and backhaul load, with future directions including energy efficiency enhancements.

Abstract

Network function virtualization leverages programmable data plane switches to deploy in-network implementable functions, to improve QoS. The memories of switches can be extended through remote direct memory access to access external memories. This paper exploits the switches external memories to place VNFs at time intervals with ultra-low latency and high bandwidth demands. The reconfiguration decision is modeled as an optimization to minimize the deployment and reconfiguration cost, while meeting the SFCs deadlines. A DRL based method is proposed to reconfigure service chains adoptable with dynamic network and traffic characteristics. To deal with slow convergence due to the complexity of deployment scenarios, static and dynamic filters are used in policy networks construction to diminish unfeasible placement exploration. Results illustrate improvement in convergence, acceptance ratio and cost.
Paper Structure (12 sections, 20 equations, 6 figures, 1 algorithm)

This paper contains 12 sections, 20 equations, 6 figures, 1 algorithm.

Table of Contents

  1. Introduction
  2. Motivation
  3. SYSTEM MODEL
  4. Optimization Formulation
  5. Objective
  6. Constraints:
  7. Delay Calculation
  8. DRL Based SFCs Reconfiguration
  9. MDP Elements
  10. Policy Network and Training
  11. Evaluation Results
  12. Conclusion and Future Work

Figures (6)

  • Figure 1: The local and external memory in PDP switches.
  • Figure 2: The scenario for external memory usage. (a) The current configuration with two SFCs. (b) The new configuration when the traffic rate of the second SFC increases so that VNF1 can not accommodate the traffic.
  • Figure 3: Policy networks. For each switch there are 2 neurons indicating Local Memory (LM) and External Memory (EM).
  • Figure 4: Topology of fat tree.
  • Figure 5: Reward variation within training.
  • ...and 1 more figures