Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge

TL;DR

This work tackles the problem of constructing anonymized network traffic matrices at line rate by integrating P4-based packet processing with High-Level Synthesis on FPGA-based SmartNICs. Using the Open Cloud Testbed and CAIDA traces, the authors implement a P4+HLS framework to extract source-destination IPs and assemble anonymized data, achieving about $95\,\text{Gbps}$ on 100G links and saturating 512-byte packets. The approach leverages an OpenNIC overlay and a P4+extern/HLS pipeline to enable stateful processing within the P4 flow, demonstrating the first AMD FPGA deployment that combines P4 and HLS for this class of network function. The work provides a practical, scalable path toward real-time anonymized graph analytics and outlines improvements for broader FPGA-side participation in the graph challenge.

Abstract

Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network researchers can create customized FPGA-based network functions and execute network tasks on accelerators directly connected to the network. A feature of the P4 language is that it is stateless; however, the FPGA implementation in this research requires state information. This is accomplished using P4 externs to describe the stateful portions of the design and to implement them on the FPGA using High-Level Synthesis (HLS). This paper demonstrates using an FPGA-based SmartNIC to efficiently extract source-destination IP address information from network packets and construct anonymized network traffic matrices for further analysis. The implementation is the first example of the combination of using P4 and HLS in developing network functions on the latest AMD FPGAs. Our design achieves a processing rate of approximately 95 Gbps with the combined use of P4 and High-level Synthesis and is able to keep up with 100 Gbps traffic received directly from the network.

Figures (6)

• Figure 1: Anonymized Network Traffic Graph Challenge Steps. Figure adapted from Jeremy2024Hpec.
• Figure 2: Overview of OCT FPGA development and workflowzink2021open
• Figure 3: Design illustration: the numbers shows the order of data flows.
• Figure 4: OpenNIC shell structure. Figure adapted from the OpenNIC shell documentation opennic
• Figure 5: Testbed Illustration