Delay-Optimum Adder Circuits with Linear Size

TL;DR

This work tackles fast binary addition under an arrival-time model, where the goal is to minimize the last output delay while controlling circuit size. It develops delay-optimized adder circuits by leveraging And-Or path circuits and an alternating-split framework, achieving sub-quadratic-size adders with delay bound $\log_2 W+3\log_2\log_2 n+4\log_2\log_2\log_2 n+const$ and, in a separate set of constructions, linear-size adders with comparable delay characteristics. A key contribution is a size-reduction framework (BS24) that linearizes sub-quadratic adders with modest delay overhead, yielding adders of $\mathcal{O}(n\log_2 n)$ and $\mathcal{O}(n\log_2\log_2 n)$ sizes, and ultimately a linear-size adder with delay near the lower bound. The results are underpinned by concrete analyses of And-Prefix and And-Or path circuits, including explicit constants and polynomial-time constructions, making the methods practically relevant for circuit designers. Overall, the paper significantly narrows the delay-gap to the information-theoretic bound for linear-size adders and provides a versatile framework to tailor size versus delay for large-scale binary addition.

Abstract

We present efficient circuits for the addition of binary numbers. We assume that we are given arrival times for all input bits and optimize the delay of the circuits, i.e.\ the time when the last output bit is computed. This contains the classical optimization of depth as a special case where all arrival times are $0$. In this model, we present, among other results, the fastest adder circuits of sub-quadratic size and the fastest adder circuits of linear size. In particular, for adding two $n$-numbers we get a circuits with linear size and delay $\log_2W+3\log_2\log_2n+4\log_2\log_2\log_2n +const$ where $\log_2W$ is a lower bound for the delay of any adder circuit (no matter what size it has).

Figures (9)

• Figure 1: Circuits realizing $((x_0\land x_1)\land x_2)\lor((x_1\land x_2)\lor x_3)$ from Example \ref{['ex1']} with arrival times in blue.
• Figure 2: Two adder circuits on $n=3$ input pairs, see Example \ref{['extrem_adders']}.
• Figure 3: Visualization of the alternating split (Theorem \ref{['thmaltsplit']}).
• Figure 4: Visualization of the adder construction of Theorem \ref{['daddercirc']} on 6 input pairs.
• Figure 5: $S(t_0,\dots,t_{n-1})$ for $n=4,6$ and $9$.

Theorems & Definitions (109)

• Definition 2.1
• Definition 2.2
• Definition 2.3
• Definition 2.4
• Lemma 2.5
• Definition 2.6
• Definition 2.7
• Theorem 2.8
• Definition 2.9
• Definition 2.10