The Lynchpin of In-Memory Computing: A Benchmarking Framework for Vector-Matrix Multiplication in RRAMs

TL;DR

This paper addresses the Von Neumann bottleneck and energy inefficiency of data movement, arguing that RRAM crossbars enable in-memory vector-matrix multiplication for large-scale data tasks. It introduces MELISO, an end-to-end VMM benchmarking framework built on NeuroSim+ to analyze error propagation across diverse RRAM device metrics. The authors perform a large-scale study using 32x32 crossbars and 1000 random inputs to characterize how memory window, weight bits, non-linearity, and C-to-C variation influence VMM errors, and identify parametric distributions that best fit the observed errors, e.g., $I_{ij} = \sum_i V_i G_{ij}$. These results guide hardware–algorithm co-design for robust memory-centric computing and motivate further exploration of optimization strategies and device engineering.

Abstract

The Von Neumann bottleneck, a fundamental challenge in conventional computer architecture, arises from the inability to execute fetch and data operations simultaneously due to a shared bus linking processing and memory units. This bottleneck significantly limits system performance, increases energy consumption, and exacerbates computational complexity. Emerging technologies such as Resistive Random Access Memories (RRAMs), leveraging crossbar arrays, offer promising alternatives for addressing the demands of data-intensive computational tasks through in-memory computing of analog vector-matrix multiplication (VMM) operations. However, the propagation of errors due to device and circuit-level imperfections remains a significant challenge. In this study, we introduce MELISO (In-Memory Linear Solver), a comprehensive end-to-end VMM benchmarking framework tailored for RRAM-based systems. MELISO evaluates the error propagation in VMM operations, analyzing the impact of RRAM device metrics on error magnitude and distribution. This paper introduces the MELISO framework and demonstrates its utility in characterizing and mitigating VMM error propagation using state-of-the-art RRAM device metrics.

Figures (5)

• Figure 1: Overview of MELISO: An end-to-end VMM benchmarking framework
• Figure 2: Effect of a) Weight Bits b) Memory Window on VMM error term (w/out non-linearity and C-to-C)
• Figure 3: Effect of Non-Linearity on VMM error term
• Figure 4: Effect of the C-to-C variation on VMM error term. a) without considering the non-linearity, b) in the presence of non-linearity, and c) Comparing variance for both cases.
• Figure 5: Effect of non-idealities on VMM performance of different device types, a)Without non-linearity and C-to-C variation, b)With non-linearity and C-to-C variation