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Peephole Optimization for Quantum Approximate Synthesis

Joseph Clark, Himanshu Thapliyal

TL;DR

A series of improvements to the final phase of this architecture, which include the addition of error awareness and a better method of approximating the correctness of the result are proposed, demonstrating that the best-performing method provides an average reduction in Total Variational Distance and Jensen-Shannon Divergence.

Abstract

Peephole optimization of quantum circuits provides a method of leveraging standard circuit synthesis approaches into scalable quantum circuit optimization. One application of this technique partitions an entire circuit into a series of peepholes and produces multiple approximations of each partitioned subcircuit. A single approximation of each subcircuit is then selected to form optimized result circuits. We propose a series of improvements to the final phase of this architecture, which include the addition of error awareness and a better method of approximating the correctness of the result. We evaluated these proposed improvements on a set of benchmark circuits using the IBMQ FakeWashington simulator. The results demonstrate that our best-performing method provides an average reduction in Total Variational Distance (TVD) and Jensen-Shannon Divergence (JSD) of 18.2% and 15.8%, respectively, compared with the Qiskit optimizer. This also constitutes an improvement in TVD of 11.4% and JSD of 9.0% over existing solutions.

Peephole Optimization for Quantum Approximate Synthesis

TL;DR

A series of improvements to the final phase of this architecture, which include the addition of error awareness and a better method of approximating the correctness of the result are proposed, demonstrating that the best-performing method provides an average reduction in Total Variational Distance and Jensen-Shannon Divergence.

Abstract

Peephole optimization of quantum circuits provides a method of leveraging standard circuit synthesis approaches into scalable quantum circuit optimization. One application of this technique partitions an entire circuit into a series of peepholes and produces multiple approximations of each partitioned subcircuit. A single approximation of each subcircuit is then selected to form optimized result circuits. We propose a series of improvements to the final phase of this architecture, which include the addition of error awareness and a better method of approximating the correctness of the result. We evaluated these proposed improvements on a set of benchmark circuits using the IBMQ FakeWashington simulator. The results demonstrate that our best-performing method provides an average reduction in Total Variational Distance (TVD) and Jensen-Shannon Divergence (JSD) of 18.2% and 15.8%, respectively, compared with the Qiskit optimizer. This also constitutes an improvement in TVD of 11.4% and JSD of 9.0% over existing solutions.
Paper Structure (10 sections, 4 figures, 3 tables, 1 algorithm)

This paper contains 10 sections, 4 figures, 3 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Proposed Methods
  3. Cascaded Error Estimation
  4. Error Aware Fidelity Evaluation
  5. Population-Based Annealing
  6. Time Complexity
  7. Configurations
  8. Results
  9. Discussion
  10. Conclusion

Figures (4)

  • Figure 1: Basic structure of the Quest framework, with three phases. Partitioning splits the circuit, expansion approximates each partition, and recombination puts approximations together to produce one or more noise resilient approximations. Recombination is the focus of this work. For the partitioning phase, we use GTQCP GTQCP, which is a much more efficient alternative to ScanPartitioner BQSKitUpdated. For the expansion phase, we use the modified LEAP compiler LEAP proposed in Quest QEst.
  • Figure 2: Improvement in Total Variational Distance with respect to the optimized initial circuit across all recombination configurations for all benchmark circuits, as a percentage. Not shown is the performance of the basic method with error awareness for HLF 5, which is -92.1%.
  • Figure 3: Improvement in Jensen-Shannon Divergence with respect to the optimized initial circuit across all recombination configurations for all benchmark circuits, as a percentage. Not shown is the performance of the basic method with error awareness for HLF 5, which is -71.1%.
  • Figure 4: Improvement in number of CNOT gates across all recombination configurations with respect to the optimized initial circuit for all benchmark circuits, as a percentage.