Accreditation Against Limited Adversarial Noise

TL;DR

The paper addresses trustworthy verification of near-term quantum computations under a limited adversarial noise model. It extends an existing accreditation protocol by introducing a cryptographic-adversarial framework with Alice, Bob, and Robert, plus redaction-based concealment and the SPSCL_beta error model, enabling robust verification without IID assumptions. The core contributions are the formal problem setting, definitions of redaction classes and CPTP lists, the design of an adversarial accreditation protocol with encrypted trap/target outputs, and a provable bound on the ideal-actual variation distance for the target circuit. This approach preserves near-term efficiency and practicality while enhancing resilience to adversarial-like noise, with potential extensions to more general noise models in hardware.

Abstract

I present an accreditation protocol (a variety of quantum verification) where error is assumed to be adversarial (in contrast to the assumption error is implemented by identical CPTP maps used in previous accreditation protocols) - albeit slightly modified to reflect physically motivated error assumptions. This is achieved by upgrading a pre-existing accreditation protocol (from [S. Ferracin et al. Phys. Rev. A 104, 042603 (2021)]) to function correctly in the face of adversarial error, with no diminution in efficiency or suitability for near-term usage.

Figures (6)

• Figure 1: An example circuit with a redacted gate (the gate with a black block, in the middle of the circuit). Note that the location of the gate (in terms of when it is applied and which qubits are affected by it) is depicted but which operation the gate represents is hidden by the black block and hence is unknown to anyone viewing this redacted circuit.
• Figure 2: Example circuits within the same redaction class, where the redaction class corresponds to the redacted circuit in Fig. \ref{['fig:redactionExample']}. Note that the circuit in Fig. \ref{['fig:redactionExample']} could be any of the above circuits if the redaction on its single-qubit gate were removed.
• Figure 3: If $\Xi_1 = [\xi_1, \xi_2, \xi_3]$ is a CPTP list used to determine the error in an execution of the top circuit in Fig. \ref{['fig:redactionClassExample']}, then Fig. \ref{['fig:CPTPDefiningErrorExample']} depicts the circuit that is actually executed. $\xi_1$ describes the error due to state preparation, $\xi_2$ describes the error due to the single-qubit gate, and $\xi_3$ describes the error due to measurement. Note that notation is slightly abused to display the CPTP maps from $\Xi$ as gates (depicting error) in a circuit. To remedy this abuse slightly CPTP maps are highlighted in red to denote they are not unitaries but are CPTP maps.
• Figure : Formal Adversarial Model: How Sets of Circuits are Executed
• Figure : Generating Trap and Target Circuits with Hidden Outputs

Theorems & Definitions (18)

• Definition 1
• Definition 2
• Definition 3
• Definition 4
• Definition 5
• Definition 6
• Lemma 1
• Definition 7
• Definition 8
• Lemma 2