A Hybrid Vectorized Merge Sort on ARM NEON

TL;DR

This paper addresses the challenge of efficient sorting on ARM NEON by introducing NEON-MS, a hybrid vectorized merge sort that is optimized for register usage, compact comparator networks, and a novel hybrid bitonic merger. The method partitions data across threads, employs an in-register sort using an optimal 16-register configuration, uses a few-comparator 16-element column sort, and employs a hybrid bitonicmerger to interleave serial and vectorized merges. Experimental results on FT2000+ show significant speedups, with NEON-MS averaging 3.8× faster than std::sort and 2.1× faster than boost::block_sort in single-thread mode, and up to 1.25× improvement over parallel boost with 64 threads; localized tests identify 16 registers as optimal. Overall, NEON-MS demonstrates architecture-aware enhancements that translate to practical performance gains for large-scale sorting on ARM NEON systems, aided by OpenMP parallelization.

Abstract

Sorting algorithms are the most extensively researched topics in computer science and serve for numerous practical applications. Although various sorts have been proposed for efficiency, different architectures offer distinct flavors to the implementation of parallel sorting. In this paper, we propose a hybrid vectorized merge sort on ARM NEON, named NEON Merge Sort for short (NEON-MS). In detail, according to the granted register functions, we first identify the optimal register number to avoid the register-to-memory access, due to the write-back of intermediate outcomes. More importantly, following the generic merge sort framework that primarily uses sorting network for column sort and merging networks for three types of vectorized merge, we further improve their structures for high efficiency in an unified asymmetry way: 1) it makes the optimal sorting networks with few comparators become possible; 2) hybrid implementation of both serial and vectorized merges incurs the pipeline with merge instructions highly interleaved. Experiments on a single FT2000+ core show that NEON-MS is 3.8 and 2.1 times faster than std::sort and boost::block\_sort, respectively, on average. Additionally, as compared to the parallel version of the latter, NEON-MS gains an average speedup of 1.25.

Figures (5)

• Figure 1: The flowchart of NEON-MS algorithm, with three improvements highlighted in blue italic, i.e., the optimal number of the used registers, sorting networks with few comparators for column sort, and three types of merges with our hybrid merging network.
• Figure 2: The workflow of the in-register sort ($W$ = 4), where each square represents a data item, with darker cells indicating larger values.
• Figure 3: Two implementations of a comparator: the source code on the left, and the respective core assembly code on the right.
• Figure 4: A 32-element bitonic merging network. The black and blue rectangles represent data swapping in vector registers, characterized by their symmetry and independent operation.
• Figure 5: Sorting Rate (ME/s: million elements per second) of different sorting methods for different data sizes.