A Hardware-Aware Gate Cutting Framework for Practical Quantum Circuit Knitting

TL;DR

This work proposes a hardware-aware framework aiming to advance the practicability of circuit knitting, and designs a cutting scheme that concurrently optimizes the number of gate cuttings and SWAP insertions during circuit cutting.

Abstract

Circuit knitting emerges as a promising technique to overcome the limitation of the few physical qubits in near-term quantum hardware by cutting large quantum circuits into smaller subcircuits. Recent research in this area has been primarily oriented towards reducing subcircuit sampling overhead. Unfortunately, these works neglect hardware information during circuit cutting, thus posing significant challenges to the follow on stages. In fact, direct compilation and execution of these partitioned subcircuits yields low-fidelity results, highlighting the need for a more holistic optimization strategy. In this work, we propose a hardware-aware framework aiming to advance the practicability of circuit knitting. Drawing a contrast with prior methodologies, the presented framework designs a cutting scheme that concurrently optimizes the number of gate cuttings and SWAP insertions during circuit cutting. In particular, we leverage the graph similarity between qubits interactions and chip layout as a heuristic guide to reduces potential SWAPs in the subsequent step of qubit routing. Building upon this, the circuit knitting framework we developed has been evaluated on several quantum algorithms, leading to reduction of total subcircuits depth by up to 64% (48% on average) compared to the state-of-the-art approach, and enhancing the relative fidelity up to 2.7$\times$.

Figures (12)

• Figure 1: Generalization of previous knitting frameworks.
• Figure 2: Example of qubit routing overhead, measured by the sum of depth of each subcircuits. "NoMap" shows compilation results with all-to-all qubit connectivity (or before compilation), "Mapped" shows the results when subcircuits are compiled with IBM Lagos (7-qubit) as backend. "Increment" shows the percentage of increased $\sum Subcircuit ~ Depth$ from "NoMap" to "Mapped", with its axis on the right.
• Figure 3: Optimization structure inside our framework. The number of cuts affects the sample overhead and postprocessing overhead with an exponential relationship (blue arrows), while graph similarity predicts the routing overhead (orange arrows). Being aware of the hardware layout, our algorithm optimize both of them.
• Figure 4: Example of CZ gate cut decomposition. There are four terms of single qubit operations, and each term represents a substitution for the original CZ gate. While the last two terms are associate with $\alpha_i$ coefficients, the mid-circuit measurement boxes stand for "post selection", i.e., the result will be kept only if "mid-circuit measurement result == $\alpha_i$".
• Figure 5: Balancing between different overheads in circuit knitting. In this motivation experiment, we cut and compile a AQFT_16 circuit to the IBM Lagos (7-qubit) quantum hardware. Y-axis shows the sum of subcircuit depth, representing the routing overhead; while X-axis shows the number of cuts related to sampling & postprocessing overhead.