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ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips

Ahmad T. Sheikh, Ali Shoker, Suhaib A. Fahmy, Paulo Esteves-Verissimo

TL;DR

ResiLogic tackles the challenge of designing fault- and intrusion-resilient chips when supply-chain actors may be untrusted. It introduces Diversity by Composability, which builds diverse, deterministic artifacts from smaller diverse modules and combines gate-level diversity with coarse-grained CMA replication. The framework leverages E-Graphs to generate diverse gate implementations, assembles them into CMAs, and then forms replicated artifacts with majority voting to mitigate Distribution, Zonal, and Compound attacks, achieving up to a fivefold resilience improvement with limited area/power impact. The results demonstrate robust resilience under all three attack models while preserving design determinism and offering tunable trade-offs between intra- and inter-diversity. This approach holds practical significance for ASIC/FPGA design under digital sovereignty constraints, enabling stronger security guarantees without prohibitive replication costs.

Abstract

A long-standing challenge is the design of chips resilient to faults and glitches. Both fine-grained gate diversity and coarse-grained modular redundancy have been used in the past. However, these approaches have not been well-studied under other threat models where some stakeholders in the supply chain are untrusted. Increasing digital sovereignty tensions raise concerns regarding the use of foreign off-the-shelf tools and IPs, or off-sourcing fabrication, driving research into the design of resilient chips under this threat model. This paper addresses a threat model considering three pertinent attacks to resilience: distribution, zonal, and compound attacks. To mitigate these attacks, we introduce the \texttt{ResiLogic} framework that exploits \textit{Diversity by Composability}: constructing diverse circuits composed of smaller diverse ones by design. This gives designer the capability to create circuits at design time without requiring extra redundancy in space or cost. Using this approach at different levels of granularity is shown to improve the resilience of circuit design in \texttt{ResiLogic} against the three considered attacks by a factor of five. Additionally, we also make a case to show how E-Graphs can be utilized to generate diverse circuits under given rewrite rules.

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips

TL;DR

ResiLogic tackles the challenge of designing fault- and intrusion-resilient chips when supply-chain actors may be untrusted. It introduces Diversity by Composability, which builds diverse, deterministic artifacts from smaller diverse modules and combines gate-level diversity with coarse-grained CMA replication. The framework leverages E-Graphs to generate diverse gate implementations, assembles them into CMAs, and then forms replicated artifacts with majority voting to mitigate Distribution, Zonal, and Compound attacks, achieving up to a fivefold resilience improvement with limited area/power impact. The results demonstrate robust resilience under all three attack models while preserving design determinism and offering tunable trade-offs between intra- and inter-diversity. This approach holds practical significance for ASIC/FPGA design under digital sovereignty constraints, enabling stronger security guarantees without prohibitive replication costs.

Abstract

A long-standing challenge is the design of chips resilient to faults and glitches. Both fine-grained gate diversity and coarse-grained modular redundancy have been used in the past. However, these approaches have not been well-studied under other threat models where some stakeholders in the supply chain are untrusted. Increasing digital sovereignty tensions raise concerns regarding the use of foreign off-the-shelf tools and IPs, or off-sourcing fabrication, driving research into the design of resilient chips under this threat model. This paper addresses a threat model considering three pertinent attacks to resilience: distribution, zonal, and compound attacks. To mitigate these attacks, we introduce the \texttt{ResiLogic} framework that exploits \textit{Diversity by Composability}: constructing diverse circuits composed of smaller diverse ones by design. This gives designer the capability to create circuits at design time without requiring extra redundancy in space or cost. Using this approach at different levels of granularity is shown to improve the resilience of circuit design in \texttt{ResiLogic} against the three considered attacks by a factor of five. Additionally, we also make a case to show how E-Graphs can be utilized to generate diverse circuits under given rewrite rules.
Paper Structure (38 sections, 2 theorems, 8 equations, 18 figures, 4 tables, 2 algorithms)

This paper contains 38 sections, 2 theorems, 8 equations, 18 figures, 4 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Related Work
  3. Threat and Fault Models
  4. Actors and Adversaries
  5. Intrusions and Faults
  6. Threats and Attacks
  7. Distribution Attack
  8. Zonal Attack
  9. Compound Attack
  10. Diversity by Composability
  11. The Quest for Resilience
  12. Diversity Levels
  13. Gate-level diversity
  14. Module-level diversity
  15. Artifact-level diversity
  16. ...and 23 more sections

Key Result

Lemma 4.1

(A Diverse CMA is deterministic) A CMA $A_i=(M_i, M_j, ...,M_N)$ whose module implementations $m_k^t$ belong to a diverse module $M_k$ is deterministic.

Figures (18)

  • Figure 1: Multi-level diversity (used in ResiLogic) has a significant impact on tolerating common mode failures.
  • Figure 2: stuck-at intrusion/fault injection.
  • Figure 3: Possible zonal attacks.
  • Figure 4: Gate-level diversity highlighting different manifestations of the $stuck-at-1$ fault.
  • Figure 5: N-bit Ripple-Carry Adder composed of diverse 4-bit adder modules.
  • ...and 13 more figures

Theorems & Definitions (5)

  • Definition 4.1: Diverse Module
  • Definition 4.2: Composable Module Artifact–CMA
  • Lemma 4.1
  • Definition 4.3: Homogeneous/Heterogeneous CMA
  • Lemma 4.2