The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs
Davide Galli, Adriano Guarisco, William Fornaciari, Matteo Matteucci, Davide Zoni
TL;DR
The paper investigates how run-time variability, especially trace desynchronization via DVFS, affects side-channel attacks on FPGA-based cryptography. It introduces a fine-grained random DVFS actuator (rDVFS) with a TRNG-based random operating point generator and dual-MMCM DFS, and validates its impact on CPA and template attacks on Artix-7 hardware using AES-128. Using metrics such as the Pearson correlation coefficient $ρ$ and guessing entropy $GE$, the study finds that dynamic frequency scaling provides the strongest resistance, while dynamic phase shift is largely ineffective and voltage scaling is vulnerable to low-frequency artifacts that HPF can mitigate. These results offer practical guidance on balancing security and performance when employing run-time variability to defend against SCA in FPGA implementations.
Abstract
To defeat side-channel attacks, many recent countermeasures work by enforcing random run-time variability to the target computing platform in terms of clock jitters, frequency and voltage scaling, and phase shift, also combining the contributions from different actuators to maximize the side-channel resistance of the target. However, the robustness of such solutions seems strongly influenced by several hyper-parameters for which an in-depth analysis is still missing. This work proposes a fine-grained dynamic voltage and frequency scaling actuator to investigate the effectiveness of recent desynchronization countermeasures with the goal of highlighting the link between the enforced run-time variability and the vulnerability to side-channel attacks of cryptographic implementations targeting FPGAs. The analysis of the results collected from real hardware allowed for a comprehensive understanding of the protection offered by run-time variability countermeasures against side-channel attacks.