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VLSI Hypergraph Partitioning with Deep Learning

Muhammad Hadir Khan, Bugra Onal, Eren Dogan, Matthew R. Guthaus

TL;DR

A new set of synthetic partitioning benchmarks that emulate real-world netlist characteristics and possess a known upper bound for solution cut quality are introduced.

Abstract

Partitioning is a known problem in computer science and is critical in chip design workflows, as advancements in this area can significantly influence design quality and efficiency. Deep Learning (DL) techniques, particularly those involving Graph Neural Networks (GNNs), have demonstrated strong performance in various node, edge, and graph prediction tasks using both inductive and transductive learning methods. A notable area of recent interest within GNNs are pooling layers and their application to graph partitioning. While these methods have yielded promising results across social, computational, and other random graphs, their effectiveness has not yet been explored in the context of VLSI hypergraph netlists. In this study, we introduce a new set of synthetic partitioning benchmarks that emulate real-world netlist characteristics and possess a known upper bound for solution cut quality. We distinguish these benchmarks with the prior work and evaluate existing state-of-the-art partitioning algorithms alongside GNN-based approaches, highlighting their respective advantages and disadvantages.

VLSI Hypergraph Partitioning with Deep Learning

TL;DR

A new set of synthetic partitioning benchmarks that emulate real-world netlist characteristics and possess a known upper bound for solution cut quality are introduced.

Abstract

Partitioning is a known problem in computer science and is critical in chip design workflows, as advancements in this area can significantly influence design quality and efficiency. Deep Learning (DL) techniques, particularly those involving Graph Neural Networks (GNNs), have demonstrated strong performance in various node, edge, and graph prediction tasks using both inductive and transductive learning methods. A notable area of recent interest within GNNs are pooling layers and their application to graph partitioning. While these methods have yielded promising results across social, computational, and other random graphs, their effectiveness has not yet been explored in the context of VLSI hypergraph netlists. In this study, we introduce a new set of synthetic partitioning benchmarks that emulate real-world netlist characteristics and possess a known upper bound for solution cut quality. We distinguish these benchmarks with the prior work and evaluate existing state-of-the-art partitioning algorithms alongside GNN-based approaches, highlighting their respective advantages and disadvantages.
Paper Structure (17 sections, 4 equations, 5 figures, 2 tables, 1 algorithm)

This paper contains 17 sections, 4 equations, 5 figures, 2 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background
  3. Synthetic Partitioning Benchmarks
  4. GNNs
  5. GAP
  6. Net Models
  7. Benchmark Implementation
  8. Methodology
  9. Evaluation of Benchmarks
  10. Evaluation of Partitioning Algorithms
  11. Graph Inference
  12. Run-Time
  13. Net Model
  14. Balanced Partitioning
  15. Graph Topology and Embedding
  16. ...and 2 more sections

Figures (5)

  • Figure 1: Our proposed benchmark generation follows the GDV of the ISPD benchmarks exactly whereas other graphs were considerably different.
  • Figure 2: The difference in cut-size increases between GAP and hMETIS/known upper bound as the problem size grows while GAP does not benefit from size-specific training.
  • Figure 3: GAP run-time is nearly constant even for moderate graph sizes while PCA feature computation can increase overall run-time but less than hMETIS.
  • Figure 4: VLSI designs use hypergraphs but the hypergraph net model significantly affects quality of results.
  • Figure 5: GAP approaches the min cut-size with balance when at least 9 PCA components are used as input features while more does not always improve the cut-size.