PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting

TL;DR

PatternPaint tackles the need for DR-clean, diverse VLSI layout patterns when data is scarce and design rules evolve. It employs a diffusion-based inpainting framework with few-shot finetuning, a template-based denoising scheme, and PCA-driven iterative generation to produce DR-compliant patterns from a small starter set. Validated on Intel 18A PDK, PatternPaint achieves DR-clean outputs and higher diversity than baselines, demonstrating a practical, production-ready path for DR-aware pattern libraries and DFM tasks. The approach reduces data requirements while maintaining legal validity, enabling rapid exploration of complex DR spaces in early technology node development.

Abstract

Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new technology nodes. However, existing training-based methods for layout pattern generation rely on large datasets. In practical scenarios, especially when developing a new technology node, obtaining such extensive layout data is challenging. Consequently, training models with large datasets becomes impractical, limiting the scalability and adaptability of prior approaches. To this end, we propose PatternPaint, a diffusion-based framework capable of generating legal patterns with limited design-rule-compliant training samples. PatternPaint simplifies complex layout pattern generation into a series of inpainting processes with a template-based denoising scheme. Furthermore, we perform few-shot finetuning on a pretrained image foundation model with only 20 design-rule-compliant samples. Experimental results show that using a sub-3nm technology node (Intel 18A), our model is the only one that can generate legal patterns in complex 2D metal interconnect design rule settings among all previous works and achieves a high diversity score. Additionally, our few-shot finetuning can boost the legality rate with 1.87X improvement compared to the original pretrained model. As a result, we demonstrate a production-ready approach for layout pattern generation in developing new technology nodes.

Figures (9)

• Figure 1: Comparison between rule-based methods, training-based methods Diffpatternwang2024chatpattern, and our PatternPaint for layout pattern generation.
• Figure 2: Squish Pattern Representation.
• Figure 3: Illustration of metal layer design rules. A selected set of design rules used in PatternPaint evaluation is shown as the advance rule set. (1) Basic Rule Set: Spacing (R1-S,R2-E)/ Width (R3-W)/ Area (R4-A) of Mx layer metal element. (2) Advance Rule Set: (R3.1-W) Only a set of discrete widths is allowed. (R1.1$~$1.4-S), the allowed spacing range is different depending on the neighboring metal widths.
• Figure 4: PatternPaint framework. It consists of: (1) few-shot finetuning, (2) initial generation, (3) template-based denoising for layout refinement, followed by a design rule checking validation, and (4) PCA-based layout & mask selection to select the next inpainting samples for iterative generation. This approach enables efficient pattern generation while ensuring design rule compliance.
• Figure 5: Illustration of Template-based Denoising. Noise at the edge is reduced by comparing new scan lines with the original scan lines (black). Here, green scan line is preserved since it is larger than a predefined threshold, and red scan line is removed.