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A Physical Layer Analysis of Entropy in Delay-Based PUFs Implemented on FPGAs

Jim Plusquellic, Jennifer Howard, Ross MacKinnon, Kristianna Hoffman, Eirini Eleni Tsiropoulou, Calvin Chan

Abstract

Physical Unclonable Functions (PUFs) leverage signal variations that occur within the device as a source of entropy. On-chip instrumentation is utilized by some PUF architectures to measure and digitize these variations, which are then processed into bitstrings and secret keys for use in security functions such as authentication and encryption. In many cases, the variations in the measured signals are introduced by a sequence of components in the circuit structure defined by the PUF architecture. In particular, the Hardware-Embedded deLay PUF (HELP) measures delay variations that occur in combinational logic paths on Field Programmable Gate Arrays (FPGAs), which are composed of a set of interconnecting wires (nodes) and look-up tables (LUTs). Previous investigations of variations in these path delays show that it is possible to derive high quality bitstrings, i.e., those which exhibit high levels of uniqueness and randomness across the device population. However, the underlying source and level of variations associated with the constituent components of the paths remain unknown. In this paper, we apply statistical averaging and differencing techniques to derive estimates for the delay variation associated with an FPGA's basic components, namely LUTs and nodes, as a means of fully characterizing the PUF's source of entropy. The analysis is carried out on a set of 50,015 path delay measurements collected from a set of 20 Xilinx Zynq 7020 SoC-class FPGAs, on which 25 identical instances of a functional unit are instantiated, for a total of 500 instances.

A Physical Layer Analysis of Entropy in Delay-Based PUFs Implemented on FPGAs

Abstract

Physical Unclonable Functions (PUFs) leverage signal variations that occur within the device as a source of entropy. On-chip instrumentation is utilized by some PUF architectures to measure and digitize these variations, which are then processed into bitstrings and secret keys for use in security functions such as authentication and encryption. In many cases, the variations in the measured signals are introduced by a sequence of components in the circuit structure defined by the PUF architecture. In particular, the Hardware-Embedded deLay PUF (HELP) measures delay variations that occur in combinational logic paths on Field Programmable Gate Arrays (FPGAs), which are composed of a set of interconnecting wires (nodes) and look-up tables (LUTs). Previous investigations of variations in these path delays show that it is possible to derive high quality bitstrings, i.e., those which exhibit high levels of uniqueness and randomness across the device population. However, the underlying source and level of variations associated with the constituent components of the paths remain unknown. In this paper, we apply statistical averaging and differencing techniques to derive estimates for the delay variation associated with an FPGA's basic components, namely LUTs and nodes, as a means of fully characterizing the PUF's source of entropy. The analysis is carried out on a set of 50,015 path delay measurements collected from a set of 20 Xilinx Zynq 7020 SoC-class FPGAs, on which 25 identical instances of a functional unit are instantiated, for a total of 500 instances.
Paper Structure (17 sections, 26 equations, 17 figures)

This paper contains 17 sections, 26 equations, 17 figures.

Table of Contents

  1. Introduction
  2. Contributions
  3. Related Work
  4. Experimental Design
  5. Functional Unit
  6. FPGA Implementation
  7. Measuring Path Delays
  8. Physical Characterization of Paths and Delays
  9. Path Node Expansion
  10. Analysis of Path Delay Variation
  11. Sources of Variation and Compensation
  12. Single Path Variation Analysis
  13. Path Delay Differences
  14. Statistics of Path Pair Differences
  15. Node Variation Analysis
  16. ...and 2 more sections

Figures (17)

  • Figure 1: Process used to convert behavioral VHDL description of a functional unit to WDDL logic style.
  • Figure 2: WDDL conversion process for an inverting gate.
  • Figure 3: Partial Vivado schematic of experimental design illustrating Clock Strobing method used to make high resolution measurements of path delays.
  • Figure 4: Implementation view of aes_mixedcol functional unit (hard macro) and the placement locations where exact copies of the hard macro were placed to create additional instances.
  • Figure 5: Definitions of FF, node, switch, net and LUT.
  • ...and 12 more figures