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A Non-Traditional Approach to Assisting Data Address Translation

Shyam Murthy, Gurindar S Sohi

TL;DR

The paper addresses data address translation bottlenecks caused by DTLB misses by introducing PC-Indexed Data Address Translation (PCAX), which uses the PC of a load to fetch PTEs from PCATs rather than from the data address. PCAX employs a two-level PCAT structure tightly coupled to the instruction path to provide translations ahead of data address calculation, augmenting but not replacing conventional DTLBs. Empirical results on ARM server traces show substantial reductions in effective CDTLB misses (roughly 2–3×) and decreases in STLB misses, with corresponding improvements in CPI and dynamic energy, while keeping storage overhead modest. The approach is designed as a no-ISA-change microarchitectural augmentation, with selective applicability to problem loads and periodic PCAT invalidation to manage freshness and activity.

Abstract

This paper proposes a novel way to assist conventional data address translation. The approach, PC-Indexed Data Address Translation (PCAX), uses the PC of a load instruction, and not a data virtual address, to obtain the page table entry (PTE) for the data accessed by a load instruction. PCAX is intended to be used for a small subset of the static loads in a program. We observe that: (i) a small subset of static loads is responsible for most of the misses in a data translation lookaside buffer (DTLB), and (ii) often a dynamic instance of a static load instruction accesses the same PTE as the last dynamic instance, and consider PCAX for this subset. With PCAX the effective miss rate of a conventional DTLB can be cut down by a factor of 2-3X in many cases, and even more in some cases. PCAX is also beneficial in reducing the number of secondary TLB (STLB) misses. Since the tables used for PCAX can be accessed alongside instruction fetch, they can be slow, yet frequently provide a valid PTE even before the data address calculation. This results in a performance improvement, and reduced data address translation energy, in most cases.

A Non-Traditional Approach to Assisting Data Address Translation

TL;DR

The paper addresses data address translation bottlenecks caused by DTLB misses by introducing PC-Indexed Data Address Translation (PCAX), which uses the PC of a load to fetch PTEs from PCATs rather than from the data address. PCAX employs a two-level PCAT structure tightly coupled to the instruction path to provide translations ahead of data address calculation, augmenting but not replacing conventional DTLBs. Empirical results on ARM server traces show substantial reductions in effective CDTLB misses (roughly 2–3×) and decreases in STLB misses, with corresponding improvements in CPI and dynamic energy, while keeping storage overhead modest. The approach is designed as a no-ISA-change microarchitectural augmentation, with selective applicability to problem loads and periodic PCAT invalidation to manage freshness and activity.

Abstract

This paper proposes a novel way to assist conventional data address translation. The approach, PC-Indexed Data Address Translation (PCAX), uses the PC of a load instruction, and not a data virtual address, to obtain the page table entry (PTE) for the data accessed by a load instruction. PCAX is intended to be used for a small subset of the static loads in a program. We observe that: (i) a small subset of static loads is responsible for most of the misses in a data translation lookaside buffer (DTLB), and (ii) often a dynamic instance of a static load instruction accesses the same PTE as the last dynamic instance, and consider PCAX for this subset. With PCAX the effective miss rate of a conventional DTLB can be cut down by a factor of 2-3X in many cases, and even more in some cases. PCAX is also beneficial in reducing the number of secondary TLB (STLB) misses. Since the tables used for PCAX can be accessed alongside instruction fetch, they can be slow, yet frequently provide a valid PTE even before the data address calculation. This results in a performance improvement, and reduced data address translation energy, in most cases.
Paper Structure (27 sections, 25 figures, 3 tables)

This paper contains 27 sections, 25 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Motivation
  3. PC-Indexed Address Translation
  4. Overview
  5. PCAT Structure and Operation
  6. Replacement in the PCATs
  7. Load Pipeline with PCATs
  8. Address bits for PCAT access
  9. PCAX Coupling with the CDTLB/STLB
  10. PCAT/CDTLB/STLB and Page Table Interactions
  11. Periodically Invalidating the PCATs
  12. Selectiveness of Loads Using PCAT
  13. Evaluation
  14. Benchmarks and Experimental Infrastructure
  15. Storage Costs
  16. ...and 12 more sections

Figures (25)

  • Figure 1: Percentage of static loads that are problem loads
  • Figure 2: Problem loads accessing same PTE
  • Figure 3: PCAT Tag and Data Entry
  • Figure 4: Relevant Portion of Load Operation
  • Figure 5: Total Data Pages Touched
  • ...and 20 more figures