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Simopt -- Simulation pass for Speculative Optimisation of FPGA-CAD flow

Eashan Wadhwa, Shanker Shreejith

TL;DR

Simopt addresses the gap between functional verification and back-end optimization by harvesting behavioural simulation metadata to drive latency-aware placement and routing in FPGA CAD flows. The approach combines Verilator-era simulation data with a modified Yosys-ABC flow, using simopt-counters, simopt-state, and a logarithmically weighted objective $A_{simopt}$ to bias placement and packing toward frequently active signals. Key contributions include the Simopt-Verilator integration, a Protobuf-based metadata dump, and a Yosys-ABC backend that improves design latency with minimal area impact, demonstrated on Verilator and EPFL benchmarks (up to 38.2% latency reduction and 5–10% routing speed-up). The framework is plug-and-play, enabling broader adoption across simulators and CAD backends and offering practical impact for reducing FPGA design iteration time, albeit with some simulation-time overhead for metadata generation.

Abstract

Behavioural simulation is deployed in CAD flow to verify the functional correctness of a Register Transfer Level (RTL) design. Metadata extracted from behavioural simulation could be used to optimise and/or speed up subsequent steps in the hardware design flow. In this paper, we propose Simopt, a tool flow that extracts simulation metadata to improve the timing performance of the design by introducing latency awareness during the placement phase and subsequently improving the routing time of the post-placed netlist using vendor tools. For our experiments, we adapt the open-source Yosys flow to perform Simopt-aware placement. Our results show that using the Simopt-pass in the design implementation flow results in up to 38.2% reduction in timing performance (latency) of the design.

Simopt -- Simulation pass for Speculative Optimisation of FPGA-CAD flow

TL;DR

Simopt addresses the gap between functional verification and back-end optimization by harvesting behavioural simulation metadata to drive latency-aware placement and routing in FPGA CAD flows. The approach combines Verilator-era simulation data with a modified Yosys-ABC flow, using simopt-counters, simopt-state, and a logarithmically weighted objective to bias placement and packing toward frequently active signals. Key contributions include the Simopt-Verilator integration, a Protobuf-based metadata dump, and a Yosys-ABC backend that improves design latency with minimal area impact, demonstrated on Verilator and EPFL benchmarks (up to 38.2% latency reduction and 5–10% routing speed-up). The framework is plug-and-play, enabling broader adoption across simulators and CAD backends and offering practical impact for reducing FPGA design iteration time, albeit with some simulation-time overhead for metadata generation.

Abstract

Behavioural simulation is deployed in CAD flow to verify the functional correctness of a Register Transfer Level (RTL) design. Metadata extracted from behavioural simulation could be used to optimise and/or speed up subsequent steps in the hardware design flow. In this paper, we propose Simopt, a tool flow that extracts simulation metadata to improve the timing performance of the design by introducing latency awareness during the placement phase and subsequently improving the routing time of the post-placed netlist using vendor tools. For our experiments, we adapt the open-source Yosys flow to perform Simopt-aware placement. Our results show that using the Simopt-pass in the design implementation flow results in up to 38.2% reduction in timing performance (latency) of the design.
Paper Structure (6 sections, 2 equations, 4 figures, 2 tables)

This paper contains 6 sections, 2 equations, 4 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Simopt-Verilator
  4. Simopt-backends
  5. Results
  6. Conclusion

Figures (4)

  • Figure 1: Traditional Verilator flow from a Verilog HDL to a C++ behavioural simulation. Verilator coins this compilation flow as verilate.
  • Figure 2: Emission of the Verilator AST to C++ behavioural simulation steps
  • Figure 3: The Simopt framework: Plug-and-use feature. Here Simopt-* can be any other framework which has integrated the Simopt encoded dump.
  • Figure 4: A graph of logarithmic scale factor vs the simopt_counters. Higher the simopt_counter, lower the variance in the scalar factor, allowing all high activations to be treated with importance