SWAP-less Implementation of Quantum Algorithms

TL;DR

This work introduces a parity-label tracking formalism that allows implementing quantum algorithms on devices with limited connectivity without qubit overhead, SWAPs, or shuttling. By leveraging an extended LHZ parity code and both spatial and temporal encodings, the authors derive resource-optimal circuits for the QFT and QAOA on linear architectures, achieving a total two-qubit gate count of $n^2-1$ and a depth of $5n-3$ for the QFT, and substantial depth reductions for QAOA with linear chains and ladder layouts. The approach yields SWAP-free implementations that outperform prior best-known linear-chain methods and offer a clear path to balancing qubit count against circuit depth via ladder configurations. Overall, parity-based compilation provides a scalable, hardware-aware strategy for near-term quantum computing on NISQ devices, with potential extensions to higher-order spin models and broader Clifford-driven circuits.

Abstract

We present a formalism based on tracking the flow of parity quantum information to implement algorithms on devices with limited connectivity without qubit overhead, SWAP operations or shuttling. Instead, we leverage the fact that entangling gates not only manipulate quantum states but can also be exploited to transport quantum information. We demonstrate the effectiveness of this method by applying it to the quantum Fourier transform (QFT) and the Quantum Approximate Optimization Algorithm (QAOA) with $n$ qubits. This improves upon all state-of-the-art implementations of the QFT on a linear nearest-neighbor architecture, resulting in a total circuit depth of ${5n-3}$ and requiring ${n^2-1}$ CNOT gates. For the QAOA, our method outperforms SWAP networks, which are currently the most efficient implementation of the QAOA on a linear architecture. We further demonstrate the potential to balance qubit count against circuit depth by implementing the QAOA on twice the number of qubits using bi-linear connectivity, which approximately halves the circuit depth.

Figures (5)

• Figure 1: Labeling of qubits demonstrating the effects of CNOT gates on the qubit encoding. The labels $P^{(1)}_{2}$ and $P^{(2)}_{2}$ of physical qubit $2$ respectively at time $\tau_{1}$ and $\tau_{2}$ are explicitly shown and used as example in the main text. The initial labels $P_j^{(0)}$ directly correspond to individual logical qubit information $\bar{Z}_{j}$ labeled $0,1$ and $2$. Furthermore, the labels change at the targets of the CNOTs according to Eq. \ref{['eq:symmetric_difference']}. The colored lines between the qubit vertices represent logical lines, indicating how the corresponding logical $X$ operator is spread out onto physical operators.
• Figure 2: (a) A unit cell of the extended LHZ code for $5$ logical qubits in two spatial dimensions. The large arrows indicate the periodic boundary conditions, i.e., joining the edges indicated by the arrows forms a closed strip with periodic labeling. For example, the qubits with labels $\{0, 3\}$, $\{0, 4\}$, $\{1, 3\}$ and $\{1, 4\}$ at the boundaries form a $Z$ stabilizer. Two different spanning lines are highlighted by the qubits and lines with thick borders, reaching from the top boundary to the bottom boundary. In the spatial picture, the colored parts correspond to overlap of a logical line with a spanning line, while in the temporal encoding they correspond to the full logical lines. The horizontal arrows indicate how the spanning line effectively evolves from left to right by applying the quantum circuit in (b), which changes the qubit labels. (b) The quantum circuit that changes the parity labels in the left spanning line to the labels in the right spanning line in (a). (c) Pictorial representation of the action of the gates $C'_{1}$ and $C'_{2}$ on the spanning lines.
• Figure 3: The QFT circuit on a linear chain using the parity label tracking. White and black rectangles represent $R_{Z}$ and $R_{X}$ rotations by the indicated angles, respectively, and gray rectangles correspond to Hadamard gates. The circles correspond to the physical qubits, and their labels denote the parities of logical qubits they carry. At the beginning and the end of the circuit, the physical qubits have a one-to-one correspondence to the logical qubits. Note that the algorithm intrinsically reverses the order of qubits.
• Figure 4: (a) The quantum circuit to implement the problem unitary $U_P$ of the QAOA with parameter $\gamma$ by means of the time-encoded parity layout, where the angles are defined as ${\Tilde{J}_{ij}=\gamma {J}_{ij}}$ and ${\Tilde{h}_{i}=\gamma {h}_{i}}$. The circuit propagates through the different spanning lines as indicated by the changing labels and logical lines (colored lines in the figure). (b) The quantum circuit to implement the mixer unitary $U_X$ with parameter $\beta$ of the QAOA. This circuit does not change the spanning line and requires ${2(n-2)}$ CNOT gates during $4$ time steps and $n$ single-qubit gates in $2$ time steps.
• Figure 5: (a) The effective evolution of two spanning lines in opposite directions for applying $U_{P}$ on a ladder architecture for ${n=6}$. The logical lines with dotted borders indicate the initial spanning line ($\tau_0)$. (b) The initialization of a second spanning line from a first spanning line by using empty qubits and $n$ CNOT gates. (c) The two spanning lines after implementing $U_{P}$, where the logical lines are delocalized. In order to allow easier implementation of $U_X$, the encoding is reduced to a single spanning line again, by decoding the second spanning line via $X$-basis measurements and conditional $Z$ gates.