Hardware Implementation of Projection-Aggregation Decoders for Reed-Muller Codes

TL;DR

The hardware implementation of UPA exhibits superior resource usage and reduced energy consumption compared to CPA for the iterative projection aggregation (IPA) decoder, highlighting a critical insight: reducing computational cost, in isolation, may not necessarily translate into hardware cost effectiveness.

Abstract

This paper presents the hardware implementation of two variants of projection-aggregation-based decoding of Reed-Muller (RM) codes, namely unique projection aggregation (UPA) and collapsed projection aggregation (CPA). Our study focuses on introducing hardware architectures for both UPA and CPA. Through thorough analysis and experimentation, we observe that the hardware implementation of UPA exhibits superior resource usage and reduced energy consumption compared to CPA for the vanilla IPA decoder. This finding underscores a critical insight: software optimizations, in isolation, may not necessarily translate into hardware cost-effectiveness.

Figures (10)

• Figure 1: Third-order IPA decoder for one iteration HashemipourTCAS2023.
• Figure 2: Block diagram of two unfolded levels of unique projection aggregation method for RM$(m,r)$Hashemipour2023.
• Figure 3: Redundancy tree and matrix $\mathbf{R}$ for RM$(5,3)$.
• Figure 4: Third-order IUPA decoder for one iteration.
• Figure 5: Output of ILP optimization for RM$(5,3)$ code with different $G$. (a) $G = 2$ and (b) $G = 4$.