Proving Cutoff Bounds for Safety Properties in First-Order Logic
Raz Lotan, Eden Frenkel, Sharon Shoham
TL;DR
This work addresses verifying safety properties of parameterized systems modeled in first-order logic (FO) by introducing a finite-domain semantics that restricts attention to finite structures. It adapts the cutoff method to FO via size-reducing simulations, enabling a reduction from unbounded domains to bounded-domain instances. A concrete FO encoding is developed to represent and validate these simulations using SMT solving, and the authors implement a tool that demonstrates the approach on diverse distributed protocols, including cases not provable by FO inductive invariants. The results indicate that finite-domain cutoffs can be effectively discovered and validated, broadening the applicability of FO verification to finite, yet unbounded, systems with practical implications for automated safety verification.
Abstract
First-order logic has been established as an important tool for modeling and verifying intricate systems such as distributed protocols and concurrent systems. These systems are parametric in the number of nodes in the network or the number of threads, which is finite in any system instance, but unbounded. One disadvantage of first-order logic is that it cannot distinguish between finite and infinite structures, leading to spurious counterexamples. To mitigate this, we offer a verification approach that captures only finite system instances. Our approach is an adaptation of the cutoff method to systems modeled in first-order logic. The idea is to show that any safety violation in a system instance of size larger than some bound can be simulated by a safety violation in a system of a smaller size. The simulation provides an inductive argument for correctness in finite instances, reducing the problem to showing safety of instances with bounded size. To this end, we develop a framework to (i) encode such simulation relations in first-order logic and to (ii) validate the simulation relation by a set of verification conditions given to an SMT solver. We apply our approach to verify safety of a set of examples, some of which cannot be proven by a first-order inductive invariant.
